{"_id":"@aloeminium108/risc-v-emulator","name":"@aloeminium108/risc-v-emulator","dist-tags":{"latest":"1.0.0"},"versions":{"1.0.0":{"name":"@aloeminium108/risc-v-emulator","version":"1.0.0","description":"An emulator for the RISC-V instruction set architecture","main":"dist/index.js","types":"dist/index.d.ts","homepage":"https://github.com/Aloeminium108/risc-v-emulator","bugs":{"url":"https://github.com/Aloeminium108/risc-v-emulator/issues"},"scripts":{"test":"npm run build; jest","build":"tsc","start":"npm run build; node ./dist"},"author":{"name":"Alice Parrish"},"license":"ISC","devDependencies":{"@types/jest":"^29.5.3","jest":"^29.6.1","ts-jest":"^29.1.1"},"gitHead":"1cec11df49ff378b15dc369f853235318d2bae56","_id":"@aloeminium108/risc-v-emulator@1.0.0","_nodeVersion":"16.20.1","_npmVersion":"8.19.4","dist":{"integrity":"sha512-IbBuhmXjWAvY6GJG2Q00nRZQ95ZC/ctmpxXueZHDn5L1MIM/VggLbD6L+o15Z7D+qRWd/rnvNfWyg7HgxifVzw==","shasum":"ba32d181efb50e0bcad97a09ea424740c08f538d","tarball":"https://registry.npmjs.org/@aloeminium108/risc-v-emulator/-/risc-v-emulator-1.0.0.tgz","fileCount":20,"unpackedSize":63447,"signatures":[{"keyid":"SHA256:jl3bwswu80PjjokCgh0o2w5c2U4LhQAE57gj9cz1kzA","sig":"MEUCIQCWFv41XMsVw/D0hH6cZK0V+vmpy4GB75cWgrdKTFokYQIgGnZBITL7u1PjuGmbNy+Vhnk4aADICaosDy72qerjqw8="}]},"_npmUser":{"name":"aloeminium108","email":"aloeasinthevera@gmail.com"},"directories":{},"maintainers":[{"name":"aloeminium108","email":"aloeasinthevera@gmail.com"}],"_npmOperationalInternal":{"host":"s3://npm-registry-packages","tmp":"tmp/risc-v-emulator_1.0.0_1689793791431_0.6203818785148763"},"_hasShrinkwrap":false}},"time":{"created":"2023-07-19T19:09:51.348Z","1.0.0":"2023-07-19T19:09:51.670Z","modified":"2023-07-19T19:09:51.952Z"},"maintainers":[{"name":"aloeminium108","email":"aloeasinthevera@gmail.com"}],"description":"An emulator for the RISC-V instruction set architecture","homepage":"https://github.com/Aloeminium108/risc-v-emulator","author":{"name":"Alice Parrish"},"bugs":{"url":"https://github.com/Aloeminium108/risc-v-emulator/issues"},"license":"ISC","readme":"# RISC-V Emulator\n\nA RISC-V Emulator that runs on JavaScript, because Atwood's Law never fails to prove itself true.\n\n**DISCLAIMER:** This package was primarily created for educational and experimental purposes. Expect bugs and missing/incomplete features.\n\n## `CPU`\n\nThe `CPU` class holds the emulation logic for a RISC-V CPU. Currently the `CPU` class only supports the RV32I base instruction set.\n\n### `registerSet`\n\n**Type:** `RegisterSet`\n\nRepresents the 32 user-level base registers. Each register can be accessed and set by its index (0-31). Registers can be accessed or set as either signed or unsigned 32-bit integers.\n\nThis property is publicly scoped mostly for debugging purposes. In general use, there is no need to directly manipulate register values through this property.\n\n### `ram`\n\n**Type:** `DataView`\n\nView of the buffer representing the RAM that the CPU has access to. The RISC-V ISA assumes the memory system is little-endian, meaning that the least significant byte of each word is stored in the lowest address. This view is initialized from the `ArrayBuffer` passed to the CPU's constructor.\n\nDirect manipulation of values in RAM is necessary for memory-mapped I/O.\n\n### `pc`\n\n**Type:** `number`\n\nProgram counter. This number represents the location of the byte in RAM that the CPU is set to read an instruction from in its next execution step.\n\nBesides debugging, this property is publicly scoped for the simulation of hardware interrupts and transfer of control to and from an operating system.\n\n### `constructor(ram: ArrayBuffer, pc: number)`\n\n`ram` - The buffer representing the RAM that the `CPU` will use to execute\n\n`pc` - The address in RAM that the `pc` should initially point to\n\nIt is expected that the `ArrayBuffer` passed as `ram` already contains whatever program is being run, and that it is large enough to contain both the machine code for the program itself and any memory addresses that may be referenced in said program.\n\n### `executionStep()`\n\nSteps the `CPU` forward by one clock cycle. Note that because the hardware is being completely abstracted here, there is no guarantee that execution of this method will perfectly align with a single clock cycle on a physical RISC-V CPU.\n\n\n## `RegisterSet`\n\nSets of user-level registers are implemented as a single `ArrayBuffer` behind the scenes. This class is meant to enforce set register widths and encapsulate expected functionality so that registers can be accessed by index without any possibility of overflow into surrounding registers or misaligned bytes during the read/write process.\n\n### `constructor(numRegisters: number)`\n\n`numRegisters` - The number of registers in the set\n\n### `getRegister(index: number): number`\n\n`index` - The index of the register being accessed\n\nreturns the value of the register as a signed 32-bit integer. The register at index 0 always returns a value of 0.\n\n### `getRegisterU(index: number): number`\n\n`index` - The index of the register being accessed\n\nreturns the value of the register as an unsigned 32-bit integer. The register at index 0 always returns a value of 0.\n\n### `setRegister(index: number, value: number): number`\n\n`index` - The index of the register being accessed\n\n`value` - The value that the register is being set to\n\nSets the value of the register at the specified `index` to `value` as a signed 32-bit integer. Setting the value of the register at index 0 has no effect.\n\n### `setRegisterU(index: number, value: number): number`\n\n`index` - The index of the register being accessed\n\n`value` - The value that the register is being set to\n\nSets the value of the register at the specified `index` to `value` as an unsigned 32-bit integer. Setting the value of the register at index 0 has no effect.\n\n## `Assembler`\n\nContains static methods for converting programs written in the RISC-V assembly language to binary machine code. These methods are currently very limited; pseudo-instructions, symbols, labels, and sections are not yet supported.\n\n### `assemble(asm: string[]): ArrayBuffer`\n\n*static*\n\n`asm` - The program in plaintext being assembled\n\nreturns an `ArrayBuffer` containing the entire program binary. The `ArrayBuffer` does not contain any space for general-purpose RAM, and so it is recommended to resize/rewrite the buffer before passing to the `CPU` constructor.\n\n### `assembleLine(asm: string): Instruction`\n\n*static*\n\n`asm` - The assembly instruction in plaintext being assembled\n\nreturns an `Instruction` object which may be recast to specific instruction types (i.e. R-Type, J-Type, etc.) for ease of manipulation and use.\n\nThis method is publicly accessible for debugging and testing purposes. In general, there is no need to directly use this method.\n\n\n","readmeFilename":"README.md"}