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RARS risc-v interpreter in JS","maintainers":[{"name":"specy.dev","email":"specy.dev@gmail.com"}],"readme":"# RiscV-js\nThis is a Typescript implementation of a RISC-V simulator made by compiling the [RARS RISC-V simulator](https://github.com/TheThirdOne/rars) to Javascript. \nIt is part of a family of javascript assembly interpreters/simulators: \n\n- MIPS: [git repo](https://github.com/Specy/mars),  [npm package](https://www.npmjs.com/package/@specy/mips)\n- RISC-V: [git repo](https://github.com/Specy/rars), [npm package](https://www.npmjs.com/package/@specy/risc-v)\n- X86: [git repo](https://github.com/Specy/x86-js), [npm package](https://www.npmjs.com/package/@specy/x86)\n- M68K: [git repo](https://github.com/Specy/s68k), [npm package](https://www.npmjs.com/package/@specy/s68k)\n\n## Usage \n\nFirst, create an instance of the simulator with `makeRiscVFromFiles`. Supply a virtual source tree and the path of its entry file. Relative `.include` paths resolve from the file containing the directive, while paths beginning with `/` resolve from the virtual root.\n\nBefore running the simulator, you must assemble and initialize it. You can then step through the program, simulate with breakpoints, or simulate with a limit.\n\n⚠️**WARNING**⚠️ You must have only one instance of the simulator at a time. Memory, registers, and other state may be shared or behave unpredictably with multiple instances.\n\n```typescript\nimport {RISCV, makeRiscVFromFiles, JsRiscV, RegisterName, BackStepAction} from '@specy/risc-v';\n\nconst files = {\n  'src/main.asm': `\n    .include \"lib/math.asm\"\n    .text\n    .globl main\n  main:\n    add_values(t2, 5, 7)\n  `,\n  'src/lib/math.asm': `\n    .macro add_values(%result, %left, %right)\n      li %result, %left\n      addi %result, %result, %right\n    .end_macro\n  `,\n} as const;\n\n// RISCV.setIs64Bit(true); // Set to 64-bit mode if needed\nconst riscvSimulator: JsRiscV = makeRiscVFromFiles(files, 'src/main.asm');\n\nriscvSimulator.assemble();\nriscvSimulator.initialize(true); // Start at 'main'\n\nwhile (!riscvSimulator.terminated) {\n  await riscvSimulator.step();\n}\n// or await riscvSimulator.simulate()\n\nconst pc = riscvSimulator.programCounter;\nconst t2 = riscvSimulator.getRegisterValue('t2');\n\nconsole.log(`Program Counter: ${pc}`);\nconsole.log(`t2: ${t2}`);\n\n// Accessing memory:\nconst data = riscvSimulator.readMemoryBytes(0xffff0000, 4); // Read 4 bytes from address 0xffff0000\nriscvSimulator.setMemoryBytes(0xffff0000, [0x01, 0x02, 0x03, 0x04]); // Write 4 bytes to address 0xffff0000\n\n// Registering Handlers (for syscalls and other events):\nriscvSimulator.registerHandler(\"printInt\", (value: number) => {\n  console.log(\"printInt syscall called with:\", value);\n});\n\n// Handlers may also be async: returning a promise suspends the simulation until it settles,\n// so IO can be backed by an async API without blocking the event loop.\nriscvSimulator.registerHandler(\"readInt\", async () => {\n  return await promptUserForANumber();\n});\n\n// Accessing the undo stack:\nconst undoStack = riscvSimulator.getUndoStack();\nundoStack.forEach(step => {\n  if (step.action === BackStepAction.REGISTER_RESTORE) {\n    console.log(`Register restored at PC ${step.pc}`);\n  }\n});\n\n\n// Simulating with breakpoints:\nconst breakpoints = [0x00400004, 0x00400008]; // Example breakpoint addresses\nawait riscvSimulator.simulateWithBreakpoints(breakpoints);\n\n//Simulating with a limit\nconst limit = 100\nawait riscvSimulator.simulateWithLimit(limit);\n\n//Simulating with breakpoints and a limit\nawait riscvSimulator.simulateWithBreakpointsAndLimit(breakpoints, limit);\n\n//Setting Register Values:\nriscvSimulator.setRegisterValue(\"t0\", 42);\n```\n\n## IO handlers\n\nEvery syscall that needs to talk to the outside world goes through a handler you register. A\nhandler can return its result directly, or return a promise of it:\n\n```typescript\nriscvSimulator.registerHandler(\"readInt\", () => 42);                  // synchronous\nriscvSimulator.registerHandler(\"readString\", () => fetchLine());      // asynchronous\n```\n\nWhen a handler returns a promise the simulation suspends at that instruction and resumes once the\npromise settles, so nothing has to be shoehorned into a synchronous API. Because of that,\n`step`, `simulate`, `simulateWithLimit`, `simulateWithBreakpoints` and\n`simulateWithBreakpointsAndLimit` all return a promise. Everything else on `JsRiscV` (registers,\nmemory, statements, the undo stack) stays synchronous.\n\nIf a handler's promise rejects, the pending `step`/`simulate*` call rejects as well, with the\nrejection reason in the message.\n\nSynchronous handlers never yield to the event loop: the simulation runs straight through, and the\nreturned promise settles on a microtask. Overlapping calls are queued and run one after another,\nnever concurrently.\n\nProgram time is a handler too, so a run can be given a clock of its own: `sleep` answers syscall 32\nand `time` answers syscall 30. A live run resolves `sleep` on a timer and returns `Date.now()` from\n`time`; a scripted run can settle `sleep` immediately, advance a virtual clock by the requested\nmilliseconds and return that clock instead, which keeps elapsed-time output reproducible.\n\n## Memory observers\n\nA memory-mapped device - a framebuffer, a keyboard register - is modelled by observing the memory\nthe program reads and writes:\n\n```ts\n// Every write in a framebuffer: (address, length, value), with the width of the store in bytes.\nconst frame = riscvSimulator.addMemoryWriteObserver(0x10010000, 0x10012ffc, (address, length, value) => {\n    screen.markDirty(address)\n})\n\n// One memory-mapped register: reads and writes, either of which may be null.\nconst receiver = riscvSimulator.addMemoryAccessObserver(\n    0xffff0004,\n    () => keyboard.consumeCharacter(),\n    null\n)\n\nriscvSimulator.removeMemoryObserver(frame)\nriscvSimulator.removeMemoryObservers()\n```\n\n*   Addresses must be word-aligned, `endAddress` is inclusive and covers its whole word, and a range\n    may not cross `0x80000000`; a registration that breaks any of these throws. Either form of a\n    high address is accepted: `0xffff0000` and `0xffff0000 | 0` name the same word.\n*   Handlers are given signed 32 bit integers, as the guest holds them: the register at\n    `0xffff000c` arrives as `-65524`, and a pixel word with its high bit set arrives negative.\n    Apply `>>> 0` wherever the unsigned form is wanted.\n*   Handlers run synchronously inside the instruction that caused the access, so they must be cheap\n    and must not write back into their own range. A returned promise is ignored, unlike an IO\n    handler's.\n*   An observer is notified *after* the access, with the value the program read or stored. A\n    register whose value is consumed by reading it must therefore be reloaded from the handler,\n    with `setPeripheralWord`, for the next read.\n*   Observers live on the simulator's memory, which assembling and initializing only clear the\n    contents of, so a registration survives `assemble()` and `initialize()` and - like a registered\n    IO handler - is shared by every `JsRiscV` instance. Notifications start once a program has been\n    assembled.\n*   `undo()` restores memory through the same stores, so an observed range reports the restored\n    values as ordinary writes and a device that follows notifications alone stays in step.\n\n## API\n\n### `RISCV` Static Class\n\nProvides static methods to initialize and create simulator instances.\n\n* `makeRiscVFromFiles(files: RISCVSourceSet, entryFile: string): JsRiscV`\n  Creates a simulator from a snapshot of a virtual source tree and its entry file. Source paths are canonical, root-relative POSIX paths. The factory is also available as `RISCV.makeRiscVFromFiles` and initializes the simulation environment when needed.\n* `RISCV.initializeRISCV(): void`\n  Initializes the core RISC-V simulation environment. Called internally by `makeRiscVFromFiles`, but can be called explicitly if needed.\n* `RISCV.getInstructionSet(): JsInstruction[]`\n  Returns an array of objects, each describing a supported RISC-V instruction (name, example, description, tokens).\n* `RISCV.setIs64Bit(is64Bit: boolean): void`\n  Sets the simulator to operate in 32-bit or 64-bit mode. This affects the instruction set.\n\n### `JsRiscv` Interface\n\nThis interface provides methods to control and interact with a RISC-V simulator instance.\n\n#### Properties\n\n* `canUndo: boolean` (Read-only): True if an undo operation can be performed.\n* `programCounter: number` (Read-only): The current value of the program counter (PC).\n* `stackPointer: number` (Read-only): The current value of the stack pointer (`$sp`).\n* `terminated: boolean` (Read-only): True if the simulation has terminated (e.g., via an exit syscall or error).\n\n#### Methods\n\n* `assemble(): RISCVAssembleResult`: Assembles the program. Returns an object containing a report, error list, and an `hasErrors` flag.\n* `initialize(startAtMain: boolean): void`: Initializes the simulator state for execution. If `startAtMain` is true, execution begins at the `main` label; otherwise, it starts at the first instruction.\n* `step(): Promise<StopReason>`: Executes a single instruction. Resolves to the reason the simulation stopped.\n* `undo(): void`: Undoes the last instruction executed, if `canUndo` is true and undo is enabled.\n* `setUndoEnabled(enabled: boolean): void`: Enables or disables the undo feature.\n* `setUndoSize(size: number): void`: Sets the maximum number of steps kept in the undo history. Must be called before assembling.\n* `simulateWithLimit(limit: number): Promise<StopReason>`: Simulates the program for a maximum of `limit` instructions. Resolves to the reason the simulation stopped.\n* `simulateWithBreakpoints(breakpoints: number[]): Promise<StopReason>`: Simulates the program until a breakpoint is reached or the program terminates. `breakpoints` is an array of memory addresses. Resolves to the reason the simulation stopped.\n* `simulateWithBreakpointsAndLimit(breakpoints: number[], limit: number): Promise<StopReason>`: Simulates until a breakpoint, limit is reached, or termination. Resolves to the reason the simulation stopped.\n* `getRegisterValue(register: RegisterName): number`: Returns the value of the specified register.\n* `setRegisterValue(register: RegisterName, value: number): void`: Sets the value of the specified register.\n* `getRegistersValues(): number[]`: Returns an array of all general-purpose register values. The order might be implementation-defined but usually corresponds to register numbers 0-31.\n* `getConditionFlags(): number[]`: Gets the 8 condition flags (if applicable, typically related to floating-point or custom extensions).\n* `registerHandler<T extends HandlerName>(name: T, handler: (...args: HandlerMap[T]['in']) => HandlerMap[T]['out'] | Promise<HandlerMap[T]['out']>): void`: Registers a handler function for a specific event (e.g., syscalls). See `HandlerName`, `HandlerMap` and [IO handlers](#io-handlers) for details.\n* `getUndoStack(): JsBackStep[]`: Returns the undo stack, an array of `JsBackStep` objects representing simulation history.\n* `readMemoryBytes(address: number, length: number): number[]`: Reads `length` bytes from memory starting at `address`. Returns an array of byte values. Notifies no memory observer: inspecting memory from the host is not the program reading it.\n* `setMemoryBytes(address: number, bytes: number[]): void`: Writes an array of `bytes` to memory starting at `address`, the way the program does: write observers are notified and, while undo is enabled, an undo step is recorded per byte.\n* `setPeripheralWord(address: number, value: number): void`: Writes one word-aligned word as a peripheral would, notifying no observer and recording no undo step. See [memory observers](#memory-observers).\n* `addMemoryWriteObserver(startAddress: number, endAddress: number, handler): number`: Observes every write in an address range. See [memory observers](#memory-observers).\n* `addMemoryAccessObserver(address: number, onRead, onWrite): number`: Observes reads and writes of one word. See [memory observers](#memory-observers).\n* `removeMemoryObserver(handle: number): void`: Removes one registration.\n* `removeMemoryObservers(): void`: Removes every registration.\n* `countMemoryObservers(): number`: The number of live registrations.\n* `getNextStatement(): JsProgramStatement | null`: Returns the next `JsProgramStatement` to be executed, or `null` if at the end.\n* `getStatementAtAddress(address: number): JsProgramStatement | null`: Gets the program statement at the given memory `address`.\n* `getStatementsAtSourceLocation(sourcePath: string, sourceLine: number): JsProgramStatement[]`: Returns every machine statement generated from an original one-based source location, in address order. Pseudo-instructions and macro calls can produce multiple results.\n* `getCompiledStatements(): JsProgramStatement[]`: Returns all machine statements after a successful assembly.\n* `getParsedStatements(): JsProgramStatement[]`: Returns the parsed statements before pseudo-instruction expansion.\n* `getTokenizedLines(): RiscvTokenizedLine[]`: Returns the expanded source stream with each line's path, one-based line number, original source, processed source, and tokens. It is available after tokenization succeeds, including when a later assembly stage fails.\n* `getCallStack(): JsRiscvStackFrame[]`: Returns the current call stack as an array of stack frame objects.\n* `getLabelAtAddress(address: number): string | null`: Returns the label name at the given memory `address`, or `null` if no label exists there.\n\n#### Helper Functions (for use with `JsRiscv`)\n\n* `registerHandlers(riscv: JsRiscv, handlers: Partial<HandlerMapFns>): void`: A utility to register multiple handlers at once.\n* `unimplementedHandler(name: HandlerName): (...args: any[]) => any`: Returns a function that throws an error indicating the handler `name` is not implemented. Useful for stubbing handlers.\n\n#### Types\n\n* `RegisterName`: Union type for RISC-V register names (e.g., `'ra'`, `'sp'`, `'a0'`, `'t0'`, etc.).\n* `RISCVSourceSet`: A read-only mapping from canonical virtual source paths to source strings.\n* `RISCVSourceLocation`: A source path and one-based source line.\n* `HandlerName`: Union type of all possible handler names (keys of `HandlerMap`).\n* `HandlerMap`: An object type mapping `HandlerName`s to their expected input argument types (`in`) and return type (`out`). This defines the signature for syscall/event handlers.\n* `HandlerMapFns`: An object type where keys are `HandlerName`s and values are the corresponding handler functions.\n* `DialogType`: Enum for message dialog types (`ERROR_MESSAGE`, `INFORMATION_MESSAGE`, `WARNING_MESSAGE`, `QUESTION_MESSAGE`).\n* `ConfirmResult`: Enum for confirm dialog results (`YES`, `NO`, `CANCEL`).\n* `BackStepAction`: Enum representing types of actions that can be undone (e.g., `MEMORY_RESTORE_WORD`, `REGISTER_RESTORE`).\n* `JsBackStep`: Interface representing an entry in the undo stack, detailing the action, parameters, and PC value.\n* `JsProgramStatement`: Interface representing an assembled instruction, including its source path, source line, address, binary/machine/assembly representations, and full original source line.\n* `JsInstructionToken`: Interface representing a token from the assembly source (value, type, and one-based source column).\n* `JsInstruction`: Interface describing a RISC-V instruction (name, example, description, token patterns).\n* `RiscvTokenizedLine`: An object containing source identity, original and processed line strings, and parsed `JsInstructionToken`s.\n* `RISCVAssembleError`: Interface describing an assembly diagnostic with its source path, one-based line and column, warning status, and structured macro expansion trace.\n* `RISCVAssembleResult`: Interface for the result of `assemble()`, containing a report string, list of `RISCVAssembleError`s, and a `hasErrors` boolean.\n* `JsRiscvStackFrame`: Interface describing a frame on the call stack (PC, target address, SP, FP, register snapshot).\n","readmeFilename":"README.md"}