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check functions. These functions generally take [a tscircuit json array](https://github.com/tscircuit/soup) and output an array of arrays for any issues found.","maintainers":[{"name":"seveibar","email":"seveibar@gmail.com"}],"readme":"# @tscircuit/checks\n\nValidity check functions. These functions generally take [a tscircuit json array](https://github.com/tscircuit/soup)\nand output an array of arrays for any issues found.\n\n[Getting Started Contributor Video](https://share.cleanshot.com/pk216661)\n\n## Function Overview\n\n| Function | Description |\n| --- | --- |\n| [`checkConnectorAccessibleOrientation`](./lib/check-connector-accessible-orientation.ts) | Returns `pcb_accessibility_error` for connectors whose orientation makes them inaccessible. |\n| [`checkTestPointAccessibility`](./lib/check-testpoint-accessibility.ts) | Returns `pcb_placement_error` when a test point is inside another component's courtyard on the same PCB side. |\n| [`checkAllPinsInComponentAreUnderspecified`](./lib/check-all-pins-in-component-are-underspecified.ts) | Returns `source_component_pins_underspecified_warning` when every pin on a chip lacks pin attributes. |\n| [`checkNoPowerPinDefined`](./lib/check-no-power-pin-defined.ts) | Returns `source_no_power_pin_defined_warning` when a chip has no pin with `requires_power=true`. |\n| [`checkNoGroundPinDefined`](./lib/check-no-ground-pin-defined.ts) | Returns `source_no_ground_pin_defined_warning` when a chip has no pin with `requires_ground=true`. |\n| [`checkSchematicComponentExcessiveVerticalPadding`](./lib/check-schematic-component-excessive-vertical-padding.ts) | Returns a `schematic_component_styling_warning` with `styling_issue_type: \"excessive_top_padding\"` or `\"excessive_bottom_padding\"` when a box-style component has more than three pin spacings of empty space above or below its left/right pins. |\n| [`checkSchematicComponentMissingReferenceDesignatorText`](./lib/check-schematic-component-missing-reference-designator-text.ts) | Returns a `schematic_component_styling_warning` with `styling_issue_type: \"missing_reference_designator_text\"` when a schematic component has no attached text matching its reference designator or display-name override. |\n| [`checkSchematicComponentPortsOutsideBody`](./lib/check-schematic-component-ports-outside-body.ts) | Returns a `schematic_component_styling_warning` with `styling_issue_type: \"ports_outside_body\"` when pins fall beyond the body edge they enter, with an actionable minimum `schHeight` or `schWidth`. |\n| [`checkDifferentNetViaSpacing`](./lib/check-different-net-via-spacing.ts) | Returns `pcb_via_clearance_error` if vias on different nets are too close together. |\n| [`checkEachPcbPortConnectedToPcbTraces`](./lib/check-each-pcb-port-connected-to-pcb-trace.ts) | Returns `pcb_trace_error` if any `source_port` is not connected to its corresponding PCB traces. |\n| [`checkEachPcbTraceNonOverlapping`](./lib/check-each-pcb-trace-non-overlapping/check-each-pcb-trace-non-overlapping.ts) | Returns `pcb_trace_error` when `pcb_trace` segments physically overlap incompatible geometry on the same layer. Pad/via near-misses are reported by the typed clearance checks instead. |\n| [`checkPcbComponentOverlap`](./lib/check-pcb-components-overlap/checkPcbComponentOverlap.ts) | Returns `pcb_footprint_overlap_error` when footprint elements from different components overlap in disallowed ways. |\n| [`checkPcbComponentsOutOfBoard`](./lib/check-pcb-components-out-of-board/checkPcbComponentsOutOfBoard.ts) | Returns `pcb_placement_error` when PCB components do not fit inside the board area. |\n| [`checkPcbCopperOverKeepout`](./lib/check-pcb-copper-over-keepout.ts) | Returns one `pcb_placement_error` per non-excluded component or via whose copper overlaps a keepout on a shared layer. |\n| [`checkPcbTracesOutOfBoard`](./lib/check-trace-out-of-board/checkTraceOutOfBoard.ts) | Returns `pcb_trace_error` when any trace segment or via extends beyond the board boundary. |\n| [`checkPadTraceClearance`](./lib/check-pad-trace-clearance.ts) | Returns `pcb_pad_trace_clearance_error` when a pad and unrelated trace have a positive gap below the minimum clearance. Physical overlaps are reported by `checkEachPcbTraceNonOverlapping`. |\n| [`checkViaTraceClearance`](./lib/check-via-trace-clearance.ts) | Returns `pcb_via_trace_clearance_error` when a via and unrelated trace have a positive gap below the minimum clearance. Physical overlaps are reported by `checkEachPcbTraceNonOverlapping`. |\n| [`checkPinMustBeConnected`](./lib/check-pin-must-be-connected.ts) | Returns `pcb_trace_error` when required source pins are not connected. |\n| [`checkSameNetViaSpacing`](./lib/check-same-net-via-spacing.ts) | Returns `pcb_via_clearance_error` if vias on the same net are closer than the allowed margin. |\n| [`checkSourceTracesHavePcbTraces`](./lib/check-source-traces-have-pcb-traces.ts) | Returns `pcb_trace_error` when source traces are missing corresponding `pcb_trace` routes. |\n| [`checkTracesAreContiguous`](./lib/check-traces-are-contiguous/check-traces-are-contiguous.ts) | Returns `pcb_trace_error` when trace endpoints are floating or do not connect as expected. |\n| [`checkViasOffBoard`](./lib/check-pcb-components-out-of-board/checkViasOffBoard.ts) | Returns `pcb_placement_error` if any PCB via lies outside or crosses the board boundary. |\n| [`checkCopperPourShorts`](./lib/check-copper-pour-shorts.ts) | Detects copper-pour contact with different-net traces, pads, plated holes, vias, and pours, respecting layers and BRep cutouts. Included in routing checks. |\n| [`checkCopperToBoardEdgeClearance`](./lib/check-copper-to-board-edge-clearance.ts) | Checks via, SMT-pad, plated-hole, and copper-pour geometry against the polygon board outline and required edge clearance. |\n\n## Aggregate check runner functions\n\n| Function | Description |\n| --- | --- |\n| [`runAllPlacementChecks`](./lib/run-all-checks.ts) | Runs placement checks (`checkCopperToBoardEdgeClearance`, `checkPcbComponentsOutOfBoard`, `checkPcbCopperOverKeepout`, `checkPcbComponentOverlap`, `checkPadPadClearance`, `checkCourtyardOverlap`, `checkConnectorAccessibleOrientation`, and `checkTestPointAccessibility`). |\n| [`runAllNetlistChecks`](./lib/run-all-checks.ts) | Runs netlist connectivity checks (currently `checkPinMustBeConnected`). |\n| [`runAllPinSpecificationChecks`](./lib/run-all-checks.ts) | Runs pin specification checks (e.g. `checkAllPinsInComponentAreUnderspecified`, `checkNoPowerPinDefined`, and `checkNoGroundPinDefined`). |\n| [`runAllSchematicChecks`](./lib/run-all-checks.ts) | Runs schematic-layout checks (`checkSchematicComponentExcessiveVerticalPadding`, `checkSchematicComponentMissingReferenceDesignatorText`, `checkSchematicComponentPortsOutsideBody`, and `checkSchematicPlacement`). |\n| [`runAllRoutingChecks`](./lib/run-all-checks.ts) | Runs all routing checks currently enabled (`checkEachPcbPortConnectedToPcbTraces`, `checkSourceTracesHavePcbTraces`, `checkEachPcbTraceNonOverlapping`, `checkCopperPourShorts`, `checkPadTraceClearance`, `checkViaTraceClearance`, same/different net via spacing, and `checkPcbTracesOutOfBoard`). Trace-obstacle pairs are classified before aggregation, so each pair produces one overlap or clearance diagnostic, never both. |\n| [`runAllChecks`](./lib/run-all-checks.ts) | Runs placement, schematic, netlist, pin specification, and routing checks and returns a combined list of issues. |\n\n## Consolidated placement overlaps\n\n`runAllPlacementChecks` and `runAllChecks` report one placement conflict per\ncomponent pair when footprint overlap causes multiple footprint, pad clearance,\nand courtyard diagnostics. The message names the components, counts the conflicts,\nand suggests moving them apart. Separate component pairs, clearance-only issues,\nstandalone elements, and unrelated routing diagnostics remain separate.\n\nThe result uses the existing `pcb_footprint_overlap_error` type and retains the\nunion of affected pad and hole IDs for rendering. The exported\n`PcbComponentOverlapError` interface adds `pcb_component_ids` and `related_errors`\nwith the original diagnostics, including measured clearances. These extra context\nfields are provided by checks; older Circuit JSON schema parsers may strip them.\n\nIndividual checks still return detailed diagnostics. Use\n`runAllPlacementChecks(circuitJson, { consolidateOverlaps: false })` to obtain raw\naggregate results, for example to apply exclusions before calling\n`consolidatePcbOverlapErrors(circuitJson, errors)`. Consolidation does not mutate\nits inputs and can be applied again when combining runners.\n\n## Implementation Details\n\n> [!NOTE]\n> It can be helpful to look at an [example soup file](./tests/assets/unrouted-soup-example.json)\n\ntscircuit soup JSON array containing elements. For checks involving source ports,\nand pcb traces here are the relevant elements (the types are produced below)\n\n> [!NOTE]\n> For the most up-to-date types, check out [@tscircuit/soup](https://github.com/tscircuit/soup)\n\n```ts\n// You can import these types from the @tscircuit/soup package e.g.\n// import type { PCBPort, PCBTrace, AnySoupElement } from \"circuit-json\"\n\nimport { z } from \"zod\"\nimport { distance } from \"../units\"\n\nexport const pcb_trace = z.object({\n  type: z.literal(\"pcb_trace\"),\n  source_trace_id: z.string().optional(),\n  pcb_component_id: z.string().optional(),\n  pcb_trace_id: z.string(),\n  route: z.array(\n    z.union([\n      z.object({\n        route_type: z.literal(\"wire\"),\n        x: distance,\n        y: distance,\n        width: distance,\n        start_pcb_port_id: z.string().optional(),\n        end_pcb_port_id: z.string().optional(),\n        layer: z.string(),\n      }),\n      z.object({\n        route_type: z.literal(\"via\"),\n        x: distance,\n        y: distance,\n        from_layer: z.string(),\n        to_layer: z.string(),\n      }),\n    ])\n  ),\n})\n\nexport type PCBTraceInput = z.input<typeof pcb_trace>\nexport type PCBTrace = z.output<typeof pcb_trace>\n\nimport { distance } from \"../units\"\nimport { layer_ref } from \"./properties/layer_ref\"\n\nexport const pcb_port = z\n  .object({\n    type: z.literal(\"pcb_port\"),\n    pcb_port_id: z.string(),\n    source_port_id: z.string(),\n    pcb_component_id: z.string(),\n    x: distance,\n    y: distance,\n    layers: z.array(layer_ref),\n  })\n  .describe(\"Defines a port on the PCB\")\n\nexport type PCBPort = z.infer<typeof pcb_port>\nexport type PCBPortInput = z.input<typeof pcb_port>\n\nexport const source_port = z.object({\n  type: z.literal(\"source_port\"),\n  pin_number: z.number().optional(),\n  port_hints: z.array(z.string()).optional(),\n  name: z.string(),\n  source_port_id: z.string(),\n  source_component_id: z.string(),\n})\n\nexport type SourcePort = z.infer<typeof source_port>\n\nexport const source_net = z.object({\n  type: z.literal(\"source_net\"),\n  source_net_id: z.string(),\n  name: z.string(),\n  member_source_group_ids: z.array(z.string()),\n  is_power: z.boolean().optional(),\n  is_ground: z.boolean().optional(),\n  is_digital_signal: z.boolean().optional(),\n  is_analog_signal: z.boolean().optional(),\n})\n\nexport type SourceNet = z.infer<typeof source_net>\nexport type SourceNetInput = z.input<typeof source_net>\n\nimport { z } from \"zod\"\n\nexport const pcb_trace_error = z\n  .object({\n    pcb_error_id: z.string(),\n    type: z.literal(\"pcb_error\"),\n    error_type: z.literal(\"pcb_trace_error\"),\n    message: z.string(),\n    pcb_trace_id: z.string(),\n    source_trace_id: z.string(),\n    pcb_component_ids: z.array(z.string()),\n    pcb_port_ids: z.array(z.string()),\n  })\n  .describe(\"Defines a trace error on the PCB\")\n\nexport type PCBTraceErrorInput = z.input<typeof pcb_trace_error>\nexport type PCBTraceError = z.infer<typeof pcb_trace_error>\n```\n\n\n### checkSameNameNetsAreConnected\n\nChecks whether source nets with exactly the same nonblank name belong to one electrical network, including across subcircuits. Returns one `source_confusing_net_name_warning` per ambiguous name with the affected `source_net_ids`. Connectivity follows source traces, shared ports, and both forms of internal component pin connections; a shared name or scoped connectivity key alone does not connect nets.\n\nIncluded in `runAllNetlistChecks` and `runAllChecks`. This checks logical source connectivity; PCB routing continuity remains a separate check.\n","readmeFilename":"README.md"}