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fanout solver with coordinated bus-layer escapes for SimpleRouteJson","maintainers":[{"name":"seveibar","email":"seveibar@gmail.com"}],"readme":"# @tscircuit/fanout-solver\n\nBGA fanout preprocessor for\n[`SimpleRouteJson`](https://github.com/tscircuit/tscircuit-autorouter).\n\n`FanoutSolver` routes every connected package pad to one shared breakout boundary\nbefore the general-purpose autorouter runs. It can put a small escape via in a\npad-to-pad channel or move an oversized via diagonally into the interstice\nbetween four pad corners. It routes every member of a bus in the same direction\nand treats each bus-layer decision atomically.\n\n## Local dogbone site matching\n\n`matchComponentDogboneViaSites(preparedBuses, geometryRules)` is exported for\ncallers that need adjacent pad-to-via escapes without boundary routing. It returns\na map from prepared connection index to a via-center point, or `null` when no\ncomplete assignment is found within the geometry/search limits. Coordinates are\nboard-world millimeters (+X right, +Y up). The function selects sites; callers\nremain responsible for trace/via emission, layer spans, board-edge checks, and\ndownstream connectivity. It does not declare signals connected to planes.\n\n`getComponentDogboneViaSiteCandidates` exposes statically legal candidates for\ndebugging/reservation; those candidates are not a mutually assigned solution.\nBoth functions and their geometry-rule/candidate types are available from the\npackage root.\n\n## Behavior\n\n- Uses `SimpleRouteJson.buses` when present. It also understands a point\n  `busId` and names such as `BUS_DDR_01`.\n- Detects rectangular pad footprints through obstacle `componentId` metadata,\n  including perimeter packages and two-pad passives.\n- Handles multiple mixed footprints inside one shared breakout boundary.\n- Routes perimeter and inner-matrix pads.\n- Uses `sharedBoundary` as the common exit rectangle. Without one, it infers a\n  shared rectangle around the source footprints selected for the buses, without\n  expanding that boundary to include destination footprints.\n- Ends every fanout trace exactly on its selected `sharedBoundary` edge. Border\n  distribution and lane spreading happen inside the rectangle, never after the\n  trace has crossed the boundary.\n- Infers one outward direction per bus from the bus endpoints, or accepts an\n  explicit direction override.\n- Accepts an additive `preferredExit` bus field for a particular edge\n  (`left`, `right`, `top`, or `bottom`) or corner (`top-left`, `top-right`,\n  `bottom-left`, or `bottom-right`). A corner chooses a compatible adjacent\n  edge and reserves the bus at that end of the border.\n- Accepts an unambiguous `exitPosition` bus field when the local pad escape and\n  final boundary edge differ. For example, `rightside_top` escapes locally\n  upward into the upper band and terminates on the right boundary, while\n  `topside_right` escapes locally rightward and terminates on the top boundary.\n- `availableCornersAndSides` can restrict every boundary-terminated bus to\n  named regions of the shared boundary. For example,\n  `['top_left', 'top_middle', 'top_right']` allows only top-edge exits;\n  `top` is an alias for `top_middle` (with matching aliases for the other\n  edges).\n- `borderDistribution: \"even\"` uses outward-only shoves to equalize\n  under-filled gaps across the occupied border interval while preserving bus\n  order, existing wider corridors, and trace/clearance pitch. The default\n  `\"preserve\"` mode stays source-aligned.\n- Supports balanced nearest-edge partitioning for package breakouts. Ties\n  alternate instead of favoring one axis; square grids distribute equally\n  across north, south, east, and west.\n- Enumerates combinations of the copper layers implied by `layerCount`.\n- Keeps a bounded beam of route alternatives for multi-connection buses, so\n  grouped power/signal lanes can backtrack across layer and track choices\n  before committing a prefix.\n- For dense fields with competing constrained layers, reserves every signal and\n  plane source escape before routing complete bus groups. Boundary repairs keep\n  exact exits and existing vias fixed; a blocked group can use its source layer\n  for transit when that layer is explicitly permitted for every bus in the group.\n- Keys route-prefix caches by both bus and layer, preserving plan uniqueness\n  when grouped-layer search changes bus order.\n- Prefers depth-cycled layer assignments: matching north/south (or east/west)\n  bus depths share a layer, and deeper pairs cycle through every available\n  escape layer. This forces a small stackup to reuse routing channels.\n- Keeps outward-edge buses on their source layer when possible. If a bus needs\n  a via, every connection in that bus receives one and moves to the same\n  assigned layer; mixed via use within a bus is never committed.\n- Accepts a bus-level `termination` target. The default\n  `{ type: \"boundary\" }` preserves the ordinary breakout contract, while\n  `{ type: \"plane\", layer: \"inner1\" }` escapes each source pad to a legal local\n  via and considers the connection complete on that plane instead of extending\n  it to the shared boundary.\n- Uses a straight pad-pair escape when the via fits. Otherwise it uses a 45°\n  four-pad interstitial escape and nested side bands that spread deeper\n  two-layer buses around already-routed outer buses.\n- `compactBusTracks` provides a trace/clearance-pitch fallback envelope when\n  the original endpoint track cannot route, so a wide pad row does not consume\n  a disproportionately wide breakout corridor.\n- Boundary tracks project onto the original downstream pad coordinates and\n  prefer their layer when legal. This lets ordered edge-pad buses make direct,\n  visibly continuous pad connections.\n- Chamfers orthogonal routing corners into 45° segments before validating and\n  emitting the fanout.\n- Honors a boundary bus `maxLengthSkew` as a hard local-fanout constraint. It\n  adds straight/45° meanders while retaining source escapes and boundary\n  endpoints, and atomically rejects an assignment when the requested skew cannot\n  fit inside that bus's shared boundary. Coordinated dense routing can tune\n  inside the pad field after reserving and checking all other copper. Bounded\n  paired shortening commits only a complete pair under its original skew limit.\n- Verifies oriented-pad, via, trace, and already-routed fanout clearance on\n  every complete candidate, independent of the routing strategy that produced\n  it.\n- Resolves `netConnectionName`, connection, port, trace, and obstacle metadata\n  into electrical-net identities. Same-net copper may merge; different-net\n  pads, traces, and vias must retain clearance on every layer they occupy.\n- `allowSameNetMerges` lets grouped branches such as VCC or GND reuse connected\n  copper instead of reserving artificial clearance from one another. It is\n  opt-in for ordinary branches; different electrical nets remain hard\n  obstacles. When dense plane escapes are staged around pre-existing all-layer\n  copper on their declared plane net, those plane branches are already\n  electrically joined and are matched as same-net copper.\n- `allowBlindAndBuriedVias` describes the host board's manufacturing rule. It\n  defaults to `true` for standalone compatibility; hosts that manufacture\n  through-all vias should pass `false`, which reserves every copper layer in\n  route planning and emitted-copper DRC while preserving each route's logical\n  layer transition.\n- Via-in-pad remains opt-in through `SimpleRouteJson.allowViaInPad === true`.\n  Undefined or false uses an offset dogbone, including plane terminations.\n- Audits route continuity, unique connection coverage, boundary exits, and\n  retained downstream endpoints before marking a solution complete.\n- `completeOriginalEndpoints` adds a bounded fail-first completion stage after\n  fanout. It first places DRC-gated interstitial capacitor escapes, then tries\n  breakout-to-pad routes with layer transitions at interior points along the\n  existing fanout copper, and finally calls the optional\n  `routeDownstreamConnections` host callback. Vias at original or moved routing\n  endpoints are rejected. A candidate is retained only when it improves\n  independently proven original endpoint connectivity and the complete emitted\n  copper remains DRC-clean.\n- Emits supplied fanout traces, via obstacles, and moved breakout endpoints in a\n  new `SimpleRouteJson`. The returned problem is ready for a downstream\n  autorouter to finish.\n\n## Install\n\nThis repository uses tscircuit's source-first GitHub package convention:\n\n```sh\nbun add https://github.com/tscircuit/fanout-solver\n```\n\n## Usage\n\n```ts\nimport {\n  AutoroutingPipelineSolver6,\n  CapacityMeshSolver,\n} from \"@tscircuit/capacity-autorouter\"\nimport { FanoutSolver } from \"@tscircuit/fanout-solver\"\n\nconst fanoutSolver = new FanoutSolver(simpleRouteJson, {\n  maxLayerCombinations: 256,\n  sharedBoundary: {\n    minX: -25,\n    maxX: 25,\n    minY: -25,\n    maxY: 25,\n  },\n  componentBounds: {\n    \"bga-01\": { minX: -4.7, maxX: 4.7, minY: -4.7, maxY: 4.7 },\n  },\n  busDirections: {\n    ddr: \"right\",\n  },\n  busExitPreferences: {\n    clocks: \"top-right\",\n  },\n  availableCornersAndSides: [\"top_left\", \"top\", \"top_right\"],\n  borderDistribution: \"even\",\n  compactBusTracks: true,\n  completeOriginalEndpoints: true,\n  routeDownstreamConnections: (inputSrj, { effort }) => {\n    const downstreamSolver = new AutoroutingPipelineSolver6(inputSrj, {\n      effort,\n    })\n    downstreamSolver.solve()\n    if (!downstreamSolver.solved) {\n      throw new Error(downstreamSolver.error ?? \"Downstream routing failed\")\n    }\n    return downstreamSolver.getOutputSimpleRouteJson().traces ?? []\n  },\n  buses: [\n    {\n      busId: \"ground\",\n      connectionNames: [\"VSS_A1\", \"VSS_A2\"],\n      direction: \"right\",\n      termination: { type: \"plane\", layer: \"inner1\" },\n    },\n  ],\n})\nfanoutSolver.solve()\n\nif (fanoutSolver.failed) {\n  throw new Error(fanoutSolver.error ?? \"Fanout failed\")\n}\n\nconst autorouter = new CapacityMeshSolver(\n  fanoutSolver.getOutputSimpleRouteJson(),\n)\nautorouter.solve()\n```\n\nCanonical exit positions are edge-first: `topside_left`, `topside_center`,\n`topside_right`, `rightside_top`, `rightside_center`, `rightside_bottom`,\n`bottomside_right`, `bottomside_center`, `bottomside_left`, `leftside_bottom`,\n`leftside_center`, `leftside_top`, and `center`. They normalize atomically into\nthe local `direction`, boundary-band `preferredExit`, and physical `exitEdge`;\nconflicting bus-level legacy fields are rejected. Existing buses that omit\n`exitPosition` retain their previous behavior. Hosts can import\n`getFanoutExitPositionConfig` to inspect the same normalized tuple without\nduplicating this mapping.\n\nThe downstream callback is optional. It lets the application choose its\nboard-level router while keeping `@tscircuit/fanout-solver` free of a runtime\nautorouter import. Returned traces are still accepted only after the fanout\nsolver's connectivity and copper-clearance checks pass.\n\nThe canonical bus input is the current `SimpleRouteJson` bus structure:\n\n```ts\n{\n  buses: [\n    {\n      busId: \"ddr\",\n      connectionNames: [\"BUS_DDR_01\", \"BUS_DDR_02\", \"BUS_DDR_03\"],\n      preferredExit: \"right\",\n      maxLengthSkew: 0.25,\n    },\n  ],\n}\n```\n\n`preferredExit` is an optional fanout extension to `SimpleRouteBus`; omitting it\nleaves ordinary `SimpleRouteJson` behavior unchanged. All listed connections\nreceive the same escape direction and target layer. If one connection cannot be\nrouted cleanly, the solver rejects that bus for the current layer assignment and\ntries another combination. `busExitPreferences` provides the same override\nwithout modifying the input object.\n\n`maxLengthSkew` is measured in millimeters of planar routed copper within this\nfanout phase. It is supported for multi-connection boundary buses. A loose or\nomitted constraint leaves the routed geometry unchanged; an impossible\nconstraint fails instead of returning a fanout that violates the declared skew.\nPlane-terminated buses reject `maxLengthSkew` because they do not have a\nboundary tuning corridor.\n\n`availableCornersAndSides` is a solver-wide hard constraint. Its directed\ncorner names distinguish the two edges meeting at a corner: `top_left` exits\nthrough the top edge, while `left_top` exits through the left edge. The complete\nset is `top_left`, `top_middle`, `top_right`, `right_top`, `right_middle`,\n`right_bottom`, `bottom_right`, `bottom_middle`, `bottom_left`, `left_bottom`,\n`left_middle`, and `left_top`. `top`, `right`, `bottom`, and `left` alias the\ncorresponding middle region. An empty list is invalid; omit the option to allow\nall edges.\n\n`termination` is another additive extension:\n\n```ts\ntype FanoutBusTermination =\n  | { type: \"boundary\" }\n  | { type: \"plane\"; layer: string }\n```\n\nA plane-targeted connection may contain only its package-pad source point. The\nsolver creates the local dogbone and via, records it in `planeTerminations`, and\nremoves the completed connection from the returned downstream\n`SimpleRouteJson`. Plane layers are fixed targets and are not included in the\nbus-layer combination search.\n\n## Output contract\n\n`getOutput()` returns:\n\n- `simpleRouteJson`: the downstream routing problem with fanout prefixes\n- `fanoutTraces`: the newly supplied pad-to-breakout traces\n- `completionTraces`: optional DRC-gated traces from breakouts to original\n  endpoints\n- `endpointCompletion`: optional independent connectivity/DRC reports and\n  bounded-search diagnostics\n- `planeTerminations`: the completed local-via connection, layer, and via data\n- `busLayerAssignments`: the selected layer for every bus\n- `busDirections`: the direction shared by each bus\n- `attempts`: score and success metadata for every tried layer combination\n- `validation`: the final geometry/connectivity report, including the number of\n  independently validated breakouts\n\n## Dataset 01\n\n`datasets/dataset01.ts` contains five deterministic footprinter samples. The\nsamples contain exactly one through five BGA footprints, and every sample is\nsolved as one `SimpleRouteJson`.\n\n| Sample      | Footprints | Pads | Connections |\n| ----------- | ---------: | ---: | ----------: |\n| `sample001` |          1 |   64 |          64 |\n| `sample002` |          2 |  100 |         100 |\n| `sample003` |          3 |  136 |         136 |\n| `sample004` |          4 |  200 |         200 |\n| `sample005` |          5 |  236 |         236 |\n\nThe Cosmos debugger provides Previous/Next controls and direct sample tabs. It\nalso stores the selected dataset and sample in the `dataset` and `sample` URL\nparameters. Each sample has one shared boundary around all of its footprints,\nand component bounds come from the exact footprinter-generated copper pad\nextents.\n\n## Dataset 31 benchmark\n\nRun `./benchmark.sh` (or `bun run benchmark`) to benchmark **all 72 dataset 31\ndirectional cases: 12 each for AM62L, RK3308, K230, i.MX6ULL, T113-S3, and AM3352** from\n[`tscircuit/dataset-fanout31-am62l`](https://github.com/tscircuit/dataset-fanout31-am62l).\nThe upstream revision is pinned in `scripts/generate-repro/package.json` and\nrecorded in every report. Other datasets remain available for regression tests\nand the debugger, but have no benchmark commands or workflows.\n\n```sh\n./benchmark.sh\n./benchmark.sh --list\n./benchmark.sh --sample 11-left-center\n./benchmark.sh --sample 13-rk3308-top-left-offset\n./benchmark.sh --sample 25-k230-top-left-offset\n./benchmark.sh --sample 37-imx6ull-top-left-offset\n./benchmark.sh --sample 49-t113s3-top-left-offset\n./benchmark.sh --sample 61-am3352-top-left-offset\n./benchmark.sh --concurrency 8 --sample-timeout-seconds 300\n```\n\nBefore timing the solver, the benchmark renders the selected upstream TSX/core\ncircuits and captures their exact fanout-solver constructor inputs into\n`benchmark-results/inputs/<sample-id>.json`. Each case retains its complete\nSoC fanout workload and the original clearance, differential-pair, and length-skew\nconstraints:\n\n| SoC | Cases | Signal connections | Plane drops | Total connections | Pad obstacles |\n| --- | ---: | ---: | ---: | ---: | ---: |\n| AM62L | 12 | 33 | 102 | 135 | 573 |\n| RK3308 | 12 | 49 | 113 | 162 | 451 |\n| K230 | 12 | 65 | 106 | 171 | 790 |\n| i.MX6ULL | 12 | 49 | 53 | 102 | 385 |\n| T113-S3 | 12 | 106 | 22 | 128 | 235 |\n| AM3352 | 12 | 205 | 117 | 322 | 529 |\n\nAM62L, RK3308, and i.MX6ULL have nine DDR signal buses each. The RK3308 samples\nuse a 355-ball SoC and 96-ball DDR3L RAM. The i.MX6ULL samples use the 289-ball\nMCIMX6Y2CVM08AB and 96-ball DDR3L RAM, retaining 47 ground and six DDR-supply\nplane drops. The K230 samples use a 390-ball SoC and two\n200-ball x16 LPDDR4 RAM packages, with 17 signal buses and six differential pairs.\nThese four families place their RAM on all four sides at three offsets per side. K230\nretains both physical RAM endpoints of its shared RESET net; the two RAM packages\nhave separate breakout regions. All 790 pads in each K230 case remain obstacles,\nincluding unused signal and supply pads.\n\nT113-S3 uses a 128-lead QFP with an exposed ground pad. Every non-NC lead and\nthe exposed pad is connected: 106 signals and 22 plane drops, with three\ndifferential pairs. Its 12 configurations rotate the package and shift bus\nbands; each configuration preserves compact bus-specific exits on all four\nedges. Signals use top, inner6, and bottom; five separate voltage/ground planes\noccupy inner1 through inner5.\n\nAM3352 uses the 324-ball AM3352BZCZD80 BGA. Its 322 operational balls connect\nto 205 signal destinations and 117 plane drops; the two NC balls remain pad\nobstacles. Its 12 configurations rotate the package and offset external\nterminals while preserving bus-specific exits on all four edges. The ten-layer\nboard uses top, inner7, inner8, and bottom for signals, with six separate\nvoltage/ground planes on inner1 through inner6 and five differential pairs.\n\nThe timed workers run **this checkout's solver**,\nnot the upstream package's released solver.\nTo capture the inputs without solving, use `bun run generate:dataset31`.\nThe optional `--dataset dataset31` flag is accepted for explicit CI invocation;\nother dataset selections are rejected.\n\nTo isolate a failure without changing pads or clearance rules, reduce a captured\ninput by bus or connection count. This is a diagnostic, not a benchmark score:\n\n```sh\nbun scripts/debug-dataset31.ts --input benchmark-results/inputs/10-left-bottom-offset.json --buses DDR_ADDR_CTRL --connection-limit 7 --output /tmp/address-seven\nbun scripts/debug-dataset31.ts --input benchmark-results/inputs/10-left-bottom-offset.json --buses DDR_ADDR_CTRL --output /tmp/address-eight\n```\n\nEach run has a hard process deadline and saves JSON progress and an SVG preview.\nUse `--dump-input <path> --capture-only` to save the exact reduced solver input\nas a regression fixture. Retained buses keep their original targets and timing\nlimits; only removed connections and their differential-pair metadata are pruned.\n\nEach sample runs in an isolated process, with up to four concurrent processes\nlocally and a **120-second hard timeout** by default. A synchronous solver hang,\nexception, or unsolved case does not prevent later samples from running.\nAssignment budgets and circuit constraints remain at each sample's defaults;\n`--max-layer-combinations` explicitly overrides only the search budget.\n\nThe ordered `benchmark-results/benchmark.json` and `benchmark.md` reports contain\nthe solver commit, dataset revision, configuration, solve totals, every sample's\nstatus and timing, and partial routing/validation counts. Reports are saved after\nevery completed sample, including the total selected count to identify incomplete runs.\nTimed-out workers do not retain their in-flight routing counts.\nEvery solved case also writes `benchmark-results/<sample-id>.svg`. These SVGs\nare committed so route changes can be reviewed in Git. A run replaces the selected\ncases' snapshots and removes their stale SVGs if they no longer solve; filtered\nruns preserve unselected snapshots. The latest JSON and Markdown reports are\nalso committed; captured inputs remain ignored. CI includes the reports, inputs,\nand SVGs in its benchmark artifacts.\nCompare reports with the same dataset revision and budgets to track progress.\nA case is solved only when every SoC connection has validated fanout: all 135\nconnections for AM62L, all 162 for RK3308, all 171 for K230, all 102 for\ni.MX6ULL, all 128 for T113-S3, or all 322 for AM3352. This covers the SoC\nfanout phase; RAM fanout and downstream inter-chip routing are separate phases.\nPartial, error, and timeout rows are benchmark results (exit 0); invalid CLI arguments or report\nI/O failures are command failures (nonzero exit).\n\n### PR comment trigger\n\nOnce `.github/workflows/benchmark.yml` is on the default branch, a repository\nwriter can comment **`/benchmark`** on an open or merged PR. The workflow\ncaptures an open PR's exact head SHA or a merged PR's immutable merge commit,\nruns all 72 dataset 31 samples on a **32-vCPU Blacksmith ARM** runner, then\nupdates a status comment with solve totals, per-sample results, and a link to\nthe complete JSON/Markdown reports and captured inputs. The Actions UI also\nsupports a manual run, optionally supplying an open or merged PR number. No\ncustom bot token is required.\n\nThe runner defaults to 32 processes and a 120-second per-sample deadline; set\nrepository variables `BENCHMARK_CONCURRENCY` and\n`BENCHMARK_SAMPLE_TIMEOUT_SECONDS` to change these. PR code runs with a read-only\ntoken and no persisted checkout credentials. A separate job uses the trusted\nworkflow revision to validate report data and post comments; it never executes\nPR code. The trusted renderer rejects legacy or mixed-dataset reports, so PR\ncomments contain only dataset 31 results. Only exact commands from non-bot users\nwith current write, maintain, or admin access are accepted.\n\n## Dataset 02\n\n`datasets/dataset02.ts` is the four-layer BGA400 stress benchmark. It routes\nevery ball in the exact footprinter string\n`bga400_grid20x20_p0.8mm_pad0.3mm_circularpads`; the debugger includes that\nstring in both the visible sample heading and browser title. The sample uses\n[JLCPCB's published 0.10/0.10 mm trace and spacing capability](https://jlcpcb.com/capabilities/pcb-capabilities/),\n0.10 mm pad/copper clearance, and standard 0.25/0.15 mm vias.\n\nExactly 100 balls and ten buses escape through each package edge. The four\nperimeter buses (76 balls) stay via-free on top. The remaining 36 buses use 324\nbus-atomic vias. Matching opposite-edge depths cycle through `inner1`,\n`inner2`, and `bottom`, so every escape layer carries twelve buses instead of\nreceiving one easy depth band.\n\nThe earlier 0.4 mm corner-interstitial case remains a dedicated regression\ntest. It cannot honestly route the full BGA400 on four layers with the retained\n0.10 mm rules: adjacent 0.15 mm via centers are 0.40 mm apart, but a crossing\n0.10 mm trace needs 0.45 mm center-to-center capacity after both clearances are\nincluded. The repeated via row is therefore a physical copper wall. The\n0.8 mm BGA400 leaves real reusable channels while still forcing a four-layer\nsolution.\n\n| Sample      | Footprints | Pads | Buses | Vias | Layers |\n| ----------- | ---------: | ---: | ----: | ---: | -----: |\n| `sample001` |          1 |  400 |    40 |  324 |      4 |\n\nEvery bus exits the shared component boundary and uses only straight or 45°\nsegments. Top, inner1, inner2, and bottom traces use distinct red, blue, green,\nand purple colors in Cosmos and the verification PNG.\n\n## Dataset 03\n\n`datasets/dataset03.ts` contains four two-layer mixed-footprint samples. Every\nsample uses the exact footprinter strings `qfn50_p0.4mm`, `res0603`, and\n`cap0603`, for 54 routed pads across three footprints and one shared boundary.\nThe QFN rotates through 0°, 90°, 180°, and 270° while the two 0603 packages\nalternate between tangential and radial placement.\n\nThe close tangential samples deliberately block two opposite top-layer QFN\nescape corridors. The solver moves each obstructed QFN side as one atomic bus\nto bottom while keeping the surrounding 0603 terminals independently routable.\nThe radial samples offset the passives toward package corners to create\nasymmetric channels without relaxing JLCPCB's 0.10 mm copper clearance or\nstandard 0.25/0.15 mm via constraints.\n\n| Sample      | Footprints | Pads | Buses | Layers |\n| ----------- | ---------: | ---: | ----: | -----: |\n| `sample001` |          3 |   54 |     8 |      2 |\n| `sample002` |          3 |   54 |     8 |      2 |\n| `sample003` |          3 |   54 |     8 |      2 |\n| `sample004` |          3 |   54 |     8 |      2 |\n\n## Dataset 04\n\n`datasets/dataset04.ts` contains five top-copper-only package-plus-decoupling\nstress cases. Every sample places exactly eight `cap0603` footprints at the\ncardinal and diagonal positions around one central package, then uses\npush-and-shove bends to move complete ordered bundles through one shared\nboundary. The `\"even\"` border-distribution option makes the exit lanes consume\ntheir available border interval consistently, and the four diagonal capacitor\npairs explicitly request their matching corners. No Dataset 04 route contains\na via or a non-top-layer wire.\n\nThe BGA cases use the exact footprinter strings\n`bga16_grid4x4_p0.8mm_pad0.3mm_circularpads`,\n`bga25_grid5x5_p1.75mm_pad0.3mm_circularpads`,\n`bga36_grid6x6_p1.5mm_pad0.3mm_circularpads`, and\n`bga64_grid8x8_p1.5mm_pad0.3mm_circularpads`. Every inner ball is connected,\ngrid-line buses remain atomic, and a sweep-line channel router pushes already\nallocated traces when a new pad row needs corridor capacity.\n\nThe final sample uses the RP2040-class footprinter string\n`qfn56_w7.8_h7.8_p0.4mm_pw0.23mm_pl0.8mm_thermalpad3.2x3.2_startingpin(topside,rightpin)_ccw`.\nThose compensated footprinter dimensions reproduce\n[Raspberry Pi's reference land pattern](https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf)\nexactly: perimeter centers at ±3.4 mm, 0.4 mm pitch, 0.8×0.23 mm pads, and a\n3.2×3.2 mm exposed pad, with no overlapping copper.\nIt routes all 56 perimeter pins, the exposed thermal pad, and all 16 capacitor\npads. The thermal-pad trace leaves on a 45° diagonal through a package corner,\ncentered between the outermost pads on its two adjacent edges. That diagonal\nchannel clears both rectangular pad corners under the same 0.10 mm trace and\n0.10 mm edge-clearance rules.\n\nAll five regressions independently verify JLCPCB's 0.10 mm trace width and\n0.10 mm copper-clearance rules, top-only routing, shared-boundary exits, inner\nBGA pad coverage, ordered push-and-shove bends, and the absence of 90° corners.\n\n| Sample      | Footprints | Routed pads | Buses | Vias | Layers |\n| ----------- | ---------: | ----------: | ----: | ---: | -----: |\n| `sample001` |          9 |          32 |    24 |    0 |      1 |\n| `sample002` |          9 |          41 |    25 |    0 |      1 |\n| `sample003` |          9 |          52 |    28 |    0 |      1 |\n| `sample004` |          9 |          80 |    32 |    0 |      1 |\n| `sample005` |          9 |          73 |    73 |    0 |      1 |\n\n## Dataset 05\n\n`datasets/dataset05.ts` uses the attached Rockchip RK3588 V1.1 ball-assignment\ndata as its checked-in source of truth. It preserves the exact 34×34 published\norientation, all 1,088 populated ball coordinates and names, and all 68\nunpopulated positions. Every generated connection and pad obstacle carries its\ncomplete source assignment as `rk3588BallAssignment` metadata.\n\nThe six-layer sample dedicates `inner1` to the 422 ground balls and `inner2` to\nthe 167 power balls. Those 589 connections end at unique 0.25/0.15 mm local\ndogbone vias. The remaining 499 signal balls are divided into short,\ndirection-consistent geometric buses and escape to the shared boundary on\n`top`, `inner3`, `inner4`, and `bottom`. All copper uses the same 0.10 mm trace\nand clearance values as the JLCPCB regressions.\n\n| Sample      | Package      | Balls | Plane terminations | Boundary signals | Layers |\n| ----------- | ------------ | ----: | -----------------: | ---------------: | -----: |\n| `sample001` | FCBGA1088L   |  1088 |                589 |              499 |      6 |\n\n## Dataset 06\n\n`datasets/dataset06.ts` preserves the 132-connection, 265-obstacle,\nsingle-layer mixed-footprint input from the clad1 RP2040 board:\n\n![clad1 RP2040 fanout reproduction](docs/images/dataset06/sample001.png)\n\nThe original reproduction failed for three independent reasons:\n\n- several serialized `source_trace_*` names belong to the same canonical\n  `connectivity_net…`, so treating those names as foreign nets creates false\n  clearance conflicts;\n- the RP2040 exposed pad is enclosed and must merge into a same-net perimeter\n  pad before following that pad's escape;\n- all 132 outward-facing exit preferences cannot coexist without crossings on\n  one layer.\n\nDataset 06 enables `singleLayerAdaptiveExits`. After the preferred\npush-and-shove attempt fails, this pass reserves short pad-escape stubs, routes\nthe remaining physical terminals together, locally merges the few\nmulti-terminal pads that do not need independent channels, and chooses\nalternate sides of the same shared boundary. The result routes all 132\nconnections on top copper with the configured 0.1 mm trace width and 0.1 mm\nclearance.\n\n## Development\n\n```sh\nbun install\nbun run typecheck\nbun test\nbun run benchmark\nbun run render:dataset\nbun run start\n```\n\nThe benchmark runs all 72 dataset 31 AM62L, RK3308, K230, i.MX6ULL, T113-S3, and AM3352 cases and\nreports solve counts, validation, and timing. `bun run start` opens all regression\ndatasets in the standard tscircuit solver debugger. `bun run\nrender:dataset` writes `graphics-debug` PNGs under one subdirectory per dataset,\nwith a red shared boundary, gray component courtyards, and green fanout-exit\nmarkers. Pass an output directory and dataset id to render one dataset, for\nexample `bun scripts/render-dataset-pngs.ts docs/images dataset06`. Failed\nregressions render their best partial attempt with a visible `INCOMPLETE`\nlabel.\n\n## Scope\n\nThis package owns the BGA pad-to-breakout prefix. It does not replace the\nboard-level autorouter or route arbitrary obstacles between the breakout\nboundary and the final destination. Its `maxLengthSkew` matching applies to the\nlocal fanout prefix; end-to-end delay matching across multiple routing phases\nstill belongs to a board-level coordinator.\n","readmeFilename":"README.md"}