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goal of this module is to find the best schematic layout for a set of `SchematicChip`s and `SchematicGroups` containing `SchematicPins` connected to each other with `SchematicTraces`","maintainers":[{"name":"seveibar","email":"seveibar@gmail.com"}],"readme":"# matchpack\n\nThe goal of this module is to find the best schematic layout for a set of `SchematicChip`s and `SchematicGroups` containing\n`SchematicPins` connected to each other with `SchematicTraces`\n\nTo do this, we use a series of solvers that are run in a pipeline. Each solver is responsible for a specific piece of\ninput preprocessing or calculation.\n\nThis is roughly the hierarchy of solvers:\n\n```\nLayoutPipelineSolver: Runs pipeline\n↳ ChipPartitionsSolver: Creates partitions (small subset groups) surrounding complex chips\n  ↳ SingleChipPartitionSolver: Creates a single partition for a single chip\n↳ PartitionPackingSolver: Packs the laid out chip partitions into a single layout\n```\n\n## Implementation Notes\n\n- There is the concept of a \"weak\" and \"strong\" connection between pins. A \"strong\" connection is one where a pin is directly assigned to another pin. A \"weak\" connection is generally a pin assigned to a net like \"GND\" or \"VCC\". Strong connections are important for layout but weak connections often determine orientation of passives (e.g. a capacitor is \"facing up\" to VCC but \"facing down\" to GND)\n- Often there are pre-laid-out designs that are passed in. This is represented by a `SchematicGroup`. We don't lay out anything inside of these groups but the inner pins are still used to compute a good packing\n","readmeFilename":"README.md"}