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for the correct positions and routing for schematic traces and net labels. For use inside [@tscircuit/core](https://github.com/tscircuit/core)","maintainers":[{"name":"seveibar","email":"seveibar@gmail.com"}],"readme":"# Schematic Trace Solver\n\nSolve for the correct positions and routing for schematic traces and net labels. For use inside [@tscircuit/core](https://github.com/tscircuit/core)\n\n[Online Playground](https://schematic-trace-solver.vercel.app) ・ [tscircuit](https://github.com/tscircuit/tscircuit) ・ [@tscircuit/core](https://github.com/tscircuit/core)\n\n<img width=\"1740\" height=\"896\" alt=\"image\" src=\"https://github.com/user-attachments/assets/53032b97-d7b5-4a00-9eab-58b58e3adecc\" />\n\n## Overview\n\nThe Schematic Trace Solver is a pipeline that figures out how to route schematic traces\nand place net labels for a given schematic layout.\n\nChips are defined by their center point, width, and height and pins.\n\nYou then pass in direct connections and net connections. Direct connections are\nexplicit pin-to-pin connections. When there's a direct connection between two\npins, there is guaranteed to be a routed trace between them.\n\nNet connections will not be routed, net labels are placed instead.\n\nThe solver first constructs minimum spanning tree to determine what pin-pairs\nto draw via the `MspConnectionPairSolver`. If there are two pins A and B that both connect to C, this phase will\ndetermine how to route traces to minimize overlap or crossings. e.g. we may\ndecide to route a trace from A to B, then B to C OR we may decide to route a\ntrace from A to C, then C to B. The pairs of traces are the mspConnectionPairs,\nthese are used in future phases.\n\nAfter the minimum spanning tree is constructed, we draw the schematic traces\nfor each mspConnectionPair via the `SchematicTraceLinesSolver`. The `TraceOverlapShiftSolver`\nthen shifts the schematic traces to make sure there are no parallel overlapping traces by\nshifting parallel traces orthogonally by a small amount.\n\nFinally, the `NetLabelPlacementSolver` places net labels for each net connection. Often\nthis requires drawing small traces to adapt to the `availableFacingDirections` of the net connection.\nIf there is crowding at the pin, we look for an available spot along the trace connected to the pin.\n\n### Inline net labels\n\nA point-to-point signal trace can be labeled *inline*: the net name is drawn\nparallel to the wire (above a horizontal trace, to the left of a vertical one)\ninstead of as an anchored label hanging off the end of it. This keeps the visual\nline between the two pins intact.\n\nInline labels are opt-in per direct connection - set `allowInlineNetLabel: true`\non the `directConnection`. The caller (usually [@tscircuit/core](https://github.com/tscircuit/core))\ndecides which connections deserve one; the solver only honors the request when\nthe connection actually got routed, since there is nothing to run parallel to\notherwise.\n\nThe `InlineNetLabelSolver` exposes `inlineNetLabelPlacements`. A net that\nreceives an inline label has its anchored `NetLabelPlacement` removed from\n`getOutput().netLabelPlacements`, so a net is never labeled twice.\n`NetLabelToTraceSolver` then replaces pairs of port-only fallback labels with\nreal traces whenever the router finds a clear path. Its `getOutput()` is the\npipeline's final output.\n\n```tsx\ndirectConnections: [\n  {\n    pinIds: [\"U1.1\", \"D1.1\"],\n    netId: \"USER_LED_ANODE\",\n    allowInlineNetLabel: true,\n  },\n]\n```\n\n## Usage\n\n```tsx\nimport { SchematicTracePipelineSolver } from \"@tscircuit/schematic-trace-solver\"\n\ntype ChipId = string\ntype PinId = string\n\nconst solver = new SchematicTracePipelineSolver({\n  chips: {\n    chipId: \"U1\",\n    center: { x: 0, y: 0 },\n    width: 1.6,\n    height: 0.6,\n    pins: [\n      {\n        pinId: \"U1.1\",\n        x: -0.8,\n        y: 0.2,\n      },\n      // ...\n    ],\n  },\n  directConnections: [\n    {\n      pinIds: [\"U1.1\", \"C1.1\"],\n      netId: \"VCC\",\n    },\n    // ...\n  ],\n  netConnections: [\n    {\n      availableFacingDirections: [\"y-\"],\n      netId: \"GND\",\n      pinIds: [\"U1.3\", \"C1.2\", \"C2.2\"],\n    },\n    // ...\n  ],\n  availableNetLabelOrientations: {\n    VCC: [\"y+\", \"y-\"],\n    GND: [\"y+\", \"y-\"],\n  },\n})\n\nsolver.solve()\n```\n\n## Development\n\n### Running locally\n\nEvery `*.page.tsx` file in the `site` directory automatically appears in the\nbrowser when you run `bun run start`. You should add pages to help you debug\nvarious solvers.\n\nBy clicking the solver name at the top of the page, you can download specific\ninputs for each solver. This can help to reproduce bugs in the solvers that\nonly appear at certain iterations.\n\n### Downloading input problems from tscircuit\n\n1. Create a test in [tscircuit/core](https://github.com/tscircuit/core)\n2. Set `DEBUG=Group_doInitialSchematicTraceRender`\n3. Run the test with `bun test`\n4. The console output will show the location of the input problem\n5. Copy the input problem and [paste it into the input debugger](https://schematic-trace-solver.vercel.app/?fixture=%7B%22path%22%3A%22site%2Fexamples%2Fexample01.page.tsx%22%7D)\n6. Download the `page.tsx` or `test.tsx` file and put it in the `site` or `tests` directories.\n\n<img width=\"1288\" height=\"1128\" alt=\"image\" src=\"https://github.com/user-attachments/assets/c067f7f9-c46c-4600-a0a4-5112440bd2f4\" />\n\n### Updating Test Snapshots\n\n1. `export BUN_UPDATE_SNAPSHOTS=1`\n2. `bun test`\n","readmeFilename":"README.md"}