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Bates <hello@grahambates.com>","license":"MIT","keywords":["68000","assembly","asm","optimization","amiga","commodore","fs-uae","win-uae"],"repository":{"url":"git+https://github.com/grahambates/m68k-tools.git","type":"git","directory":"packages/68kcounter"},"description":"68000 ASM source code cycle counter","maintainers":[{"name":"gigabates","email":"hello@grahambates.com"}],"readme":"![Logo](images/icon.png)\n\n# 68k Counter\n\nAnalyses 68000 assembly source to profile resource and size data. For each instruction it will tell you.\n\n- CPU cycles\n- Bus read cycles\n- Bus write cycles\n- Size in bytes\n\n## Usage:\n\n### Web app\n\nYou can try out the tool in a <a href=\"https://68kcounter-web.vercel.app/\">web-based version</a>.\n\n### CLI\n\nTo analyse a source file run:\n\n`npx 68kcounter mysource.s`\n\nThis will output each line prefixed with profile data in the following format:\n\n`[cycles]([reads]/[writes]) [size]`\n\nSee `npx 68kcounter --help` for more options.\n\n### Target CPU\n\nThe counter targets the **68000** by default. Pass `--cpu 68020` to select the\n68020 (or `--cpu 68030` for the 68030), or declare it in the source with a `machine mc68020` (or bare `mc68020`)\ndirective, which overrides the flag for that file.\n\n> **68020 status:** 68020 timings are transcribed from the MC68020 User's\n> Manual (§8.2). Because 68020 timing depends on the instruction cache, the\n> manual gives a cache-case and a worst-case (cache miss) figure. A single case\n> is reported — **worst case by default**, or the cache case with `--cache`.\n> (This keeps a line's value list meaning the same as on the 68000: one value\n> per outcome, e.g. a branch's taken / not-taken.) The manual's best case\n> assumes pipeline overlap between instructions and is not modelled. 68020 bus\n> cycles are shown as `reads/prefetch/writes` (operand reads and\n> instruction-stream prefetches are counted separately — both matter for bus\n> contention), whereas the 68000 shows `reads/writes` with instruction fetches\n> folded into reads. The **full 68020 integer instruction set** is covered,\n> including the 68020-only additions: bit-field (`bfextu`, `bfins`, …), 64-bit\n> `mul.l`/`div.l`, `chk2`/`cmp2`, `cas`/`cas2`, `pack`/`unpk`, `bkpt`, `rtd`,\n> `extb`, and the supervisor moves `movec`/`moves`. FPU (68881/68882) and\n> PMMU instructions are out of scope — they parse and are shown with sizes but\n> without a timing.\n\n### VS Code extension\n\nAvailable as <a href=\"https://marketplace.visualstudio.com/items?itemName=gigabates.68kcounter\">VS Code extension</a> to provide live annotations and totals.\n\n![Output window screenshot](https://raw.githubusercontent.com/grahambates/m68k-tools/main/apps/68kcounter-vscode/images/demo.gif)\n\n## Macros and repeats\n\nA macro defined in the file is expanded where it is called, and the expansion is\ncounted, with each expanded line shown against the call. Arguments are\nsubstituted as text, as the assembler does: `\\1`-`\\9`, `\\0` (the size the macro\nwas called with), `NARG`, `\\#`, `\\?n`, the `\\.`, `\\+` and `\\-` selectors and `\\@`\nfor a label unique to each call. A numbered argument the call does not give is\nempty, and `\\10` is `\\1` followed by a zero: arguments past nine are `\\a` to `\\z`\nand only in Devpac mode. `REPT` bodies are counted once per repetition.\n\nConditional assembly is not evaluated, so both arms of an `IF` are counted. A macro\ndefined in another file is not seen: a call to one adds nothing to the totals, and\nonly on the 68040 and 68060 is it flagged as untimed.\n\n`dc`, `dcb` and `ds` written without a size are words. A count that is not a\nnumber, or a constant the file does not define, is counted as nothing.\n\nSymbols keep their case, as an assembler has them unless told otherwise: `Foo` and `foo`\nare different constants, and a macro is called by the name it was defined with. Pass\n`{ caseSensitive: false }` to `parse` for a project assembled with `vasm -nocase`.\n\nA backslash in a string is an ordinary character, so `dc.b \"a\\n\"` is three bytes. Pass\n`{ escapeSequences: true }` for a project assembled with `vasm -esc`, where it is two.\n\nConditional assembly is not evaluated: every arm of an `IF` is counted, since each is a path the code may take. A constant assigned in a conditional block that has different values in different arms is unknown after the block, so anything sized by it counts as nothing, and does not take the last arm's value.\n\n## Limitations:\n\n- Because it analyses your pre-assembled source, it can't take into account\n  optimisations made by your assembler.\n- Total timings for a whole file are pretty meaningless as it doesn't take\n  into account branching etc, but it can be useful for smaller blocks.\n- Where timings are based on an 'n' multiplier from an immediate value, it\n  will parse simple expressions but doesn't currently substitute constants\n  defined elsewhere.\n- FPU and PMMU cycle timings are not modelled. See the 68020 timing assumptions above.\n\n### 68030 timings\n\nSelect `--cpu 68030`, `{ cpu: \"68030\" }` in the library, or `machine mc68030` in source. `--cache` / `{ cacheModel: \"cache\" }` selects the instruction-cache case. The default (`cacheModel: \"worst\"`, retained for API compatibility) selects the **average no-cache case**, not an absolute worst case.\n\nThe data comes from Motorola's [MC68030 User's Manual, section 11.6](https://www.nxp.com/docs/en/reference-manual/MC68030UM-P2.pdf). It assumes two-clock reads/writes and aligned operands. Timings include operand reads, instruction prefetches and writes as separate columns. Operation and effective-address costs are added without head/tail overlap; totals are isolated-instruction estimates, not pipeline simulation. Data-cache hits, MMU table walks, bus contention and additional wait states are not modelled.\n\nCovered families include MOVE/MOVEM/MOVEP, arithmetic and logic, shifts/rotates, bit operations, register bitfields, conditional branches, calls/returns, and common control instructions. Data-dependent multiply/divide use the manual's maximum values; variable shifts retain their possible outcomes. Full-format word/long displacements and memory-indirect pre/post-indexing are supported, including PC-relative sources, omitted bases, and MOVE destinations. Known displacements use the smallest encoding that fits unless an explicit `.w` or `.l` displacement width is provided. Explicit suppressed-register aliases such as `za0` remain unsupported. Unresolved indexed or memory-indirect displacements are left untimed because their encoding cannot be determined. Memory bitfields, CAS2, FPU and MMU timings are not provided. Unsupported forms do not fall back to another CPU's timing data. Byte-size estimation includes full-format and memory-indirect extension words for resolved displacements. Suppressed-register aliases and unresolved complex operands still require improved parser/encoding support; their byte sizes remain estimates.\n\nThe HTML timing transcription was used as a cross-reference. The manual distinguishes brief and full extension-word rows that have similar textual operand spellings. Its corrected CMPI memory bus counts and displacement prefetch counts are used here. Head/tail values remain available in the cited source for future overlap modelling.\n\n## Development\n\nRequires Node.js 22.15.1 or later at runtime. Use the root-pinned Node version for development. From the monorepo root, run `pnpm install --frozen-lockfile`, `pnpm --filter m68k-parser build`, then `pnpm --filter 68kcounter build` and `pnpm --filter 68kcounter test`.\n\n## License\n\n[MIT](LICENSE).\n\n## Module formats\n\nESM imports and CommonJS `require` are supported through conditional exports, with matching TypeScript declarations. Existing CommonJS file paths remain available. ESM consumers receive the native `.mjs` entry point.\n\n### 68040 and 68060 cached references\n\nSelect `--cpu 68040` / `--cpu 68060`, the matching library `cpu` option, or a `machine mc68040` / `machine mc68060` directive. These CPUs currently always use cached reference costs, regardless of `--cache` or `cacheModel`. Both instruction and data accesses are assumed to hit their caches, with aligned operands. No memory-system or uncached estimate is provided.\n\nThe tables are based on [MC68040UM §10.4–6](https://www.nxp.com/docs/en/reference-manual/MC68040UM.pdf) and [MC68060UM §10.4–14](https://www.nxp.com/docs/en/data-sheet/MC68060UM.pdf). The 040 clock column reports the manual's execution-stage lead + base cost; JSON/library results preserve the separate address-calculation and execution fields in `timing.reference.stages`. Pipeline stages overlap, so those fields must not be added together. The 060 reports the manual's instruction-execution reference, without instruction pairing. Branch prediction alternatives have separate labels; word division uses the published maximum cost.\n\nParentheses show **operand reads/writes**, not external bus transfers or DMA contention. Totals are reference sums, not elapsed sequence times. When reference costs occur, use `totals.timingGroups` (also used by the CLI/extension) rather than the legacy combined `min`/`max` fields, particularly when source directives mix CPU models. These sums must not be used alone to claim a replacement sequence is faster.\n\nInitial coverage includes MOVE/MOVEA/MOVEQ, common arithmetic and logic, register and memory shifts/rotates, comparisons, clear/negate, branches, calls/returns and address calculations. Full-format and memory-indirect costs are supported for covered families. Both CPUs cover ordinary bit operations and word/long MOVEM loads and stores. Bitfields, FPU/MMU operations, cache maintenance, locked accesses, exception handling and several miscellaneous/control-register forms remain untimed. There is no fallback for emulated or unsupported instructions. Missing coverage is exposed as `timingUnavailable` on a line and `incomplete` on its totals; macro expansions preserve this information. The remaining complex-address byte-size limitations described above still apply.\n","readmeFilename":""}