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AND MPL-2.0)","homepage":"https://github.com/falsandtru/dw-cache","keywords":["cache","lru","lfu","arc"],"repository":{"type":"git","url":"git+https://github.com/falsandtru/dw-cache.git"},"description":"The highest performance constant complexity cache algorithm.","maintainers":[{"name":"falsandtru","email":"falsandtru@gmail.com"}],"readme":"# Dual Window Cache\n\n![CI](https://github.com/falsandtru/dw-cache/workflows/CI/badge.svg)\n\nThe highest performance constant complexity cache algorithm.\n\n## Maintenance\n\nThe source code is maintained on the next source repository.\n\nhttps://github.com/falsandtru/spica\n\n## Properties\n\nGenerally superior and almost flawless.\n\n- ***Highest performance***\n  - High hit ratio\n    - ***Highest hit ratio of all the general-purpose cache algorithms.***\n      - W-TinyLFU is basically not a general-purpose cache algorithm due to some problems.\n        - W-TinyLFU is not a general-purpose cache algorithm *without dynamic window and incremental reset*.\n        - W-TinyLFU is impossible to efficiently implement *without pointer addresses or fast hash functions*.\n        - W-TinyLFU has a lower hit ratio for keys other than a single numeric type.\n        - W-TinyLFU's benchmark settings are not described (Especially suspicious with OLTP).\n    - ***Highest engineering hit ratio of all the advanced cache algorithms.***\n      - As a result of engineering efficiency.\n  - Low time overhead (High throughput)\n    - Use only two lists.\n  - Low latency\n    - Constant time complexity.\n    - No batch processing like LIRS, TinyLFU, and W-TinyLFU.\n  - Parallel suitable\n    - Separated lists are suitable for lock-free processing.\n- Efficient\n  - Low memory usage\n    - Largest cache size per memory size of all the advanced cache algorithms.\n    - Constant extra space complexity.\n    - Retain only keys of resident entries (No history).\n  - Immediate release of evicted keys\n    - Primary cache algorithm in the standard library must release memory immediately.\n  - Low space overhead\n    - Add only two smallest fields to entries.\n- High resistance\n  - Scan, loop, and burst resistance\n- Few tradeoffs\n  - Not the highest hit ratio\n    - Highest hit ratio of each workload is resulted by W-TinyLFU or ARC.\n  - Statistical accuracy dependent\n    - Too smaller capacity than appropriate can degrade hit ratio.\n      - The amount of available information decreases at an accelerating rate as cache size decreases.\n      - The more complex the statistical method, the greater the impact of the decrease in the amount of information.\n    - Minimum operating unit is 0.02% of cache size.\n      - 5,000 or more is the recommended cache size to satisfy this point.\n    - Very small cache size reduces operating precision.\n      - 200 or more is the recommended cache size to satisfy this point.\n    - On discontinuous workloads, TLRU is better.\n  - No tradeoffs other than hit ratio\n    - Other advanced cache algorithms have some tradeoffs such as spike latency by linear time complexity, delayed memory release by linear space complexity, or implementability.\n      - Other advanced cache algorithms cannot generally replace LRU due to these tradeoffs.\n\n## Tradeoffs\n\nNote that LIRS and TinyLFU are risky cache algorithms.\n\n- LRU\n  - Low performance\n  - No resistance\n    - **Scan access clears all entries.**\n- TLRU\n  - Middle performance\n    - Lower hit ratio than DWC.\n  - Limited resistance\n    - Limited loop resistance.\n- DWC\n  - Not the highest hit ratio\n  - Statistical accuracy dependent\n- ARC\n  - Middle performance\n  - Inefficient\n    - 2x key size.\n  - High overhead\n    - 4 lists.\n  - Few resistance\n    - No loop resistance.\n- LIRS\n  - Extremely inefficient\n    - ***3-2,500x key size.***\n  - Spike latency\n    - ***Bulk deletion of low-frequency entries takes linear time.***\n  - Vulnerable algorithm\n    - ***Continuous cache misses for the last LIR entry or the HIR entries explode key size.***\n      - https://issues.redhat.com/browse/ISPN-7171\n      - https://issues.redhat.com/browse/ISPN-7246\n- TinyLFU\n  - Incomplete algorithm\n    - **TinyLFU is just a vulnerable incomplete base-algorithm of W-TinyLFU.**\n    - *Burst access saturates Bloom filters.*\n    - TinyLFU is worse than LRU in theory.\n  - Language dependent\n    - **Impossible to efficiently implement without pointer addresses or fast hash functions.**\n  - High overhead\n    - Read and write average 40 array elements per access.\n  - Restricted delete operation\n    - Bloom filters don't support delete operation.\n    - *Frequent delete operations degrade performance.*\n  - Spike latency\n    - ***Whole reset of Bloom filters takes linear time.***\n  - Hit ratio degradation in general use\n    - Different hash keys can be obtained from the same key since memory addresses are used for hash keys such as strings.\n    - Impossible to distinguish between different keys of different types that are the same hash key since hash keys have no type.\n    - The impact varies depending on the OS, language, implementation, etc., and cannot be predicted without individual investigation.\n  - Vulnerable algorithm\n    - *Burst access degrades performance.*\n- W-TinyLFU\n  - Language dependent\n    - **Impossible to efficiently implement without pointer addresses or fast hash functions.**\n  - High overhead\n    - Read and write average 40 array elements per access.\n  - Restricted delete operation\n    - Bloom filters don't support delete operation.\n    - *Frequent delete operations degrade performance.*\n  - Hit ratio degradation in general use\n    - Different hash keys can be obtained from the same key since memory addresses are used for hash keys such as strings.\n    - Impossible to distinguish between different keys of different types that are the same hash key since hash keys have no type.\n    - The impact varies depending on the OS, language, implementation, etc., and cannot be predicted without individual investigation.\n  - Spike latency\n    - ***Whole reset of Bloom filters takes linear time.***\n\n## Strategies\n\n- Dynamic partition\n- Sampled history injection\n- Transitive wide MRU with cyclic replacement\n\n## Efficiency\n\nTLRU and TRC are abbreviations for TrueLRU (spica/tlru).\n\n### Mathematical efficiency\n\nSome different cache algorithms require extra memory space to retain evicted keys.\nLinear time complexity indicates the existence of batch processing.\nNote that admission algorithm doesn't work without eviction algorithm.\n\n|Algorithm|Type |Time complexity<br>(Worst case)|Space complexity<br>(Extra)|Key size|Data structures|\n|:-------:|:---:|:------:|:------:|:----------:|:-----:|\n|LRU      |Evict|Constant|Constant|     1x     |1 list |\n|TLRU     |Evict|Constant|Constant|     1x     |1 list |\n|DWC      |Evict|Constant|Constant|     1x     |2 lists|\n|ARC      |Evict|Constant|Linear  |     2x     |4 lists|\n|LIRS     |Evict|Linear  |Linear  |**3-2,500x**|2 lists|\n|TinyLFU  |Admit|Linear  |Linear  |*~1-10x*<br>(8bit * 10N * 4)|5 arrays|\n|W-TinyLFU|Admit|Linear  |Linear  |*~1-10x*<br>(8bit * 10N * 4)|1 list<br>4 arrays|\n\nhttps://github.com/ben-manes/caffeine/wiki/Efficiency<br>\nhttps://github.com/zhongch4g/LIRS2/blob/master/src/replace_lirs_base.cc\n\n### Engineering efficiency\n\nA pointer is 8 bytes, bool and int8 are each 1 byte in C.\n\n#### 8 byte key and value (int64, float64, 8 chars)\n\nIn-memory cache, memoize, etc.\n\n|Algorithm|Entry overhead|Key size|Total per entry|Attenuation coefficient|\n|:-------:|-------------:|-------:|--------------:|----------------------:|\n|LRU      |      16 bytes|      1x|       32 bytes|                100.00%|\n|TLRU     |      16 bytes|      1x|       32 bytes|                100.00%|\n|DWC      |      17 bytes|      1x|       33 bytes|                 96.96%|\n|ARC      |      17 bytes|      2x|       58 bytes|                 55.17%|\n|LIRS     |      33 bytes|      3x|      131 bytes|                 24.42%|\n|LIRS     |      33 bytes|     10x|      418 bytes|                  7.65%|\n|TinyLFU  |      56 bytes|      1x|       72 bytes|                 44.44%|\n|W-TinyLFU|      56 bytes|      1x|       72 bytes|                 44.44%|\n\n#### 32 byte key and 8 byte value (Session ID / ID)\n\nIn-memory KVS, etc.\n\n|Algorithm|Entry overhead|Key size|Total per entry|Attenuation coefficient|\n|:-------:|-------------:|-------:|--------------:|----------------------:|\n|LRU      |      16 bytes|      1x|       56 bytes|                100.00%|\n|TLRU     |      16 bytes|      1x|       56 bytes|                100.00%|\n|DWC      |      17 bytes|      1x|       57 bytes|                 98.24%|\n|ARC      |      17 bytes|      2x|       88 bytes|                 63.63%|\n|LIRS     |      33 bytes|      3x|      203 bytes|                 27.58%|\n|LIRS     |      33 bytes|     10x|      658 bytes|                  8.51%|\n|TinyLFU  |      56 bytes|      1x|       96 bytes|                 58.33%|\n|W-TinyLFU|      56 bytes|      1x|       96 bytes|                 58.33%|\n\n#### 16 byte key and 512 byte value (Domain / DNS packet)\n\nDNS cache server, etc.\n\n|Algorithm|Entry overhead|Key size|Total per entry|Attenuation coefficient|\n|:-------:|-------------:|-------:|--------------:|----------------------:|\n|LRU      |      16 bytes|      1x|      544 bytes|                100.00%|\n|TLRU     |      16 bytes|      1x|      544 bytes|                100.00%|\n|DWC      |      17 bytes|      1x|      545 bytes|                 99.81%|\n|ARC      |      17 bytes|      2x|      578 bytes|                 94.11%|\n|LIRS     |      33 bytes|      3x|      659 bytes|                 82.54%|\n|LIRS     |      33 bytes|     10x|    1,002 bytes|                 54.29%|\n|TinyLFU  |      56 bytes|      1x|      584 bytes|                 93.15%|\n|W-TinyLFU|      56 bytes|      1x|      584 bytes|                 93.15%|\n\n## Resistance\n\nLIRS's burst resistance means the resistance to continuous cache misses for the last LIR entry or the HIR entries.\nTLRU's loop resistance is limited to initial only.\n\n|Algorithm|Type |Scan|Loop|Burst|\n|:-------:|:---:|:--:|:--:|:---:|\n|LRU      |Evict|    |    |  ✓ |\n|TLRU     |Evict| ✓ |  ✓ | ✓  |\n|DWC      |Evict| ✓ |  ✓ | ✓  |\n|ARC      |Evict| ✓ |     | ✓  |\n|LIRS     |Evict| ✓ |  ✓ |     |\n|TinyLFU  |Admit| ✓ |  ✓ |     |\n|W-TinyLFU|Admit| ✓ |  ✓ | ✓  |\n\n### Loop resistance\n\nDWC automatically adjusts the history size according to the loop size.\n\n|Algorithm|Method    |Duration |Layout|History size|Resistance|Efficiency|\n|:-------:|:--------:|:-------:|:----:|-----------:|---------:|---------:|\n|TLRU     |Eventual  |Initial  |Inner |        100%|     > 10x|  > 1,000%|\n|DWC      |Statistics|Permanent|Inner |          8%|        4x|    5,000%|\n|DWC      |Statistics|Permanent|Inner |         14%|       10x|    7,142%|\n|DWC      |Statistics|Permanent|Inner |        100%|       96x|    9,600%|\n|LIRS     |Log       |Permanent|Outer |300-250,000%|  3-2,500x|      100%|\n|TinyLFU  |Hash      |Permanent|Outer |        500%|        4x|       80%|\n|W-TinyLFU|Hash      |Permanent|Outer |        500%|        4x|       80%|\n\n## Hit ratio\n\nNote that another cache algorithm sometimes changes the parameter values per workload to get a favorite result as the paper of TinyLFU has changed the window size of W-TinyLFU.\n\n- DWC's results are measured by the same default parameter values.\n- Other results are measured by the simulator in Caffeine.\n  - https://github.com/ben-manes/caffeine/wiki/Efficiency\n  - https://docs.google.com/spreadsheets/d/1G3deNz1gJCoXBE2IuraUSwLE7H_EMn4Sn2GU0HTpI5Y (https://github.com/jedisct1/rust-arc-cache/issues/1)\n\n1. Set the datasets to `./benchmark/trace` (See `./benchmark/ratio.ts`).\n    - https://github.com/dgraph-io/benchmarks\n    - https://traces.cs.umass.edu/index.php/Storage/Storage\n2. Run `npm i`.\n3. Run `npm run bench`.\n4. Click the DEBUG button to open a debug tab.\n5. Close the previous tab.\n6. Press F12 key to open devtools.\n7. Select the console tab.\n\n<!--\n// https://www.chartjs.org/docs/latest/charts/line.html\n\nconst config = {\n  type: 'line',\n  data: data,\n  options: {\n    scales: {\n        y: {\n            min: 0,\n        },\n    },\n    plugins: {\n      title: {\n        display: true,\n        text: 'WL'\n      }\n    }\n  },\n};\n-->\n\n### WS1\n\n<!--\nconst data = {\n  labels: [1e6, 2e6, 3e6, 4e6, 5e6, 6e6, 7e6, 8e6],\n  datasets: [\n    {\n      label: 'Optimal',\n      data: [27.31, 41.28, 51.04, 57.8, 62.72, 65.85, 67.22, 67.22],\n    },\n    {\n      label: 'LRU',\n      data: [2.95, 6.09, 9.63, 21.6, 33.92, 45.74, 54.89, 61.4],\n      borderColor: Utils.color(0),\n    },\n    {\n      label: 'ARC',\n      data: [8.05, 14.49, 23.62, 31.18, 39.63, 49.82, 57.78, 62.19],\n      borderColor: Utils.color(6),\n    },\n    {\n      label: 'DWC',\n      data: [10.56, 20.78, 30.21, 38.93, 46.85, 53.50, 58.89, 62.93],\n      borderColor: Utils.color(2),\n    },\n    {\n      label: 'TrueLRU',\n      data: [8.09, 18.03, 26.92, 35.88, 44.19, 51.66, 57.70, 62.46],\n      borderColor: Utils.color(1),\n    },\n    {\n      label: 'LIRS',\n      data: [12.74, 18.65, 29.05, 39.08, 47.68, 54.81, 59.9, 63.57],\n      borderColor: Utils.color(3),\n    },\n    {\n      label: 'W-TinyLFU',\n      data: [11.93, 23.08, 32.87, 41.45, 48.92, 55.15, 59.82, 63.45],\n      borderColor: Utils.color(8),\n    },\n    {\n      label: 'TinyLFU',\n      data: [11.55, 23.23, 33.08, 41.5, 49.2, 55.27, 59.96, 63.69],\n      borderColor: Utils.color(4),\n    },\n  ]\n};\n-->\n\n![image](https://github.com/falsandtru/dw-cache/assets/3143368/34c53f79-913c-45f7-904c-a40eb36cedf8)\n\nW-TinyLFU, (TinyLFU) > (LIRS), DWC > TLRU > ARC > LRU\n\n```\nWS1 1,000,000\nLRU hit ratio 2.95%\nTRC hit ratio 8.09%\nDWC hit ratio 10.56%\nDWC - LRU hit ratio delta 7.61%\n\nWS1 2,000,000\nLRU hit ratio 6.08%\nTRC hit ratio 18.03%\nDWC hit ratio 20.78%\nDWC - LRU hit ratio delta 14.69%\n\nWS1 3,000,000\nLRU hit ratio 9.63%\nTRC hit ratio 26.92%\nDWC hit ratio 30.21%\nDWC - LRU hit ratio delta 20.58%\n\nWS1 4,000,000\nLRU hit ratio 21.59%\nTRC hit ratio 35.88%\nDWC hit ratio 38.93%\nDWC - LRU hit ratio delta 17.33%\n\nWS1 5,000,000\nLRU hit ratio 33.91%\nTRC hit ratio 44.19%\nDWC hit ratio 46.85%\nDWC - LRU hit ratio delta 12.93%\n\nWS1 6,000,000\nLRU hit ratio 45.74%\nTRC hit ratio 51.66%\nDWC hit ratio 53.50%\nDWC - LRU hit ratio delta 7.76%\n\nWS1 7,000,000\nLRU hit ratio 54.89%\nTRC hit ratio 57.70%\nDWC hit ratio 58.89%\nDWC - LRU hit ratio delta 3.99%\n\nWS1 8,000,000\nLRU hit ratio 61.40%\nTRC hit ratio 62.46%\nDWC hit ratio 62.93%\nDWC - LRU hit ratio delta 1.53%\n```\n\n### WS2\n\n<!--\nconst data = {\n  labels: [1e6, 2e6, 3e6, 4e6, 5e6, 6e6, 7e6, 8e6],\n  datasets: [\n    {\n      label: 'Optimal',\n      data: [29.68, 46.08, 58.2, 67.41, 74.54, 79.86, 83.72, 86.44],\n    },\n    {\n      label: 'LRU',\n      data: [2.91, 6.2, 10.1, 23.46, 37.94, 51.69, 63.81, 73.12],\n      borderColor: Utils.color(0),\n    },\n    {\n      label: 'ARC',\n      data: [15.06, 26.23, 30.87, 38.66, 48.03, 56.23, 66.8, 75.28],\n      borderColor: Utils.color(6),\n    },\n    {\n      label: 'DWC',\n      data: [12.74, 24.21, 35.02, 44.82, 54.07, 62.40, 69.48, 75.77],\n      borderColor: Utils.color(2),\n    },\n    {\n      label: 'TrueLRU',\n      data: [9.28, 19.86, 30.05, 40.41, 50.39, 60.05, 69.29, 76.33],\n      borderColor: Utils.color(1),\n    },\n    {\n      label: 'LIRS',\n      data: [15.18, 20.39, 32.43, 44.38, 55.23, 64.56, 72.1, 78.04],\n      borderColor: Utils.color(3),\n    },\n    {\n      label: 'W-TinyLFU',\n      data: [15.47, 28.79, 40.63, 51.03, 60.29, 67.66, 73.69, 78.35],\n      borderColor: Utils.color(8),\n    },\n    {\n      label: 'TinyLFU',\n      data: [14.17, 28.67, 41.03, 51.52, 60.63, 68.1, 73.94, 78.39],\n      borderColor: Utils.color(4),\n    },\n  ]\n};\n-->\n\n![image](https://github.com/falsandtru/dw-cache/assets/3143368/036c7bc4-705d-43c6-8874-accbbdd2c2d4)\n\nW-TinyLFU, (TinyLFU) > (LIRS), DWC > TLRU > ARC > LRU\n\n```\nWS2 1,000,000\nLRU hit ratio 2.91%\nTRC hit ratio 9.28%\nDWC hit ratio 12.74%\nDWC - LRU hit ratio delta 9.82%\n\nWS2 2,000,000\nLRU hit ratio 6.19%\nTRC hit ratio 19.86%\nDWC hit ratio 24.21%\nDWC - LRU hit ratio delta 18.01%\n\nWS2 3,000,000\nLRU hit ratio 10.09%\nTRC hit ratio 30.05%\nDWC hit ratio 35.02%\nDWC - LRU hit ratio delta 24.92%\n\nWS2 4,000,000\nLRU hit ratio 23.45%\nTRC hit ratio 40.41%\nDWC hit ratio 44.82%\nDWC - LRU hit ratio delta 21.36%\n\nWS2 5,000,000\nLRU hit ratio 37.94%\nTRC hit ratio 50.39%\nDWC hit ratio 54.07%\nDWC - LRU hit ratio delta 16.13%\n\nWS2 6,000,000\nLRU hit ratio 51.69%\nTRC hit ratio 60.05%\nDWC hit ratio 62.40%\nDWC - LRU hit ratio delta 10.71%\n\nWS2 7,000,000\nLRU hit ratio 63.81%\nTRC hit ratio 69.29%\nDWC hit ratio 69.48%\nDWC - LRU hit ratio delta 5.66%\n\nWS2 8,000,000\nLRU hit ratio 73.11%\nTRC hit ratio 76.33%\nDWC hit ratio 75.77%\nDWC - LRU hit ratio delta 2.66%\n```\n\n### F1\n\n<!--\nconst data = {\n  labels: [2500, 5000, 7500, 10000, 12500, 15000, 17500, 20000],\n  datasets: [\n    {\n      label: 'Optimal',\n      data: [38.49, 41.77, 43.96, 45.65, 47.13, 48.38, 49.5, 50.52],\n    },\n    {\n      label: 'LRU',\n      data: [27.74, 30.56, 32.18, 33.27, 34.19, 34.97, 35.62, 36.17],\n      borderColor: Utils.color(0),\n    },\n    {\n      label: 'ARC',\n      data: [30.35, 33.42, 35.04, 36.37, 37.28, 37.81, 38.52, 38.98],\n      borderColor: Utils.color(6),\n    },\n    {\n      label: 'DWC',\n      data: [24.70, 29.18, 32.20, 34.66, 36.22, 37.19, 37.87, 38.32],\n      borderColor: Utils.color(2),\n    },\n    {\n      label: 'TrueLRU',\n      data: [27.48, 31.52, 34.04, 35.57, 36.72, 37.60, 38.32, 38.82],\n      borderColor: Utils.color(1),\n    },\n    {\n      label: 'LIRS',\n      data: [27.42, 31.75, 33.42, 35.06, 35.89, 36.58, 37.22, 37.75],\n      borderColor: Utils.color(3),\n    },\n    {\n      label: 'W-TinyLFU',\n      data: [22.87, 27.6, 30.1, 31.71, 32.65, 33.47, 34.09, 33.92],\n      borderColor: Utils.color(8),\n    },\n    {\n      label: 'TinyLFU',\n      data: [19.77, 23.43, 25.2, 27.18, 28.05, 28.73, 29.5, 30.06],\n      borderColor: Utils.color(4),\n    },\n  ]\n};\n-->\n\n![image](https://github.com/falsandtru/dw-cache/assets/3143368/95ba67d7-a3e2-4277-814c-47fcb8c1637b)\n\nARC > SLRU, TLRU > (LIRS), DWC > LRU > W-TinyLFU > TinyLFU\n\n```\nF1 2,500\nLRU hit ratio 27.74%\nTRC hit ratio 27.48%\nDWC hit ratio 24.70%\nDWC - LRU hit ratio delta -3.03%\n\nF1 5,000\nLRU hit ratio 30.55%\nTRC hit ratio 31.52%\nDWC hit ratio 29.18%\nDWC - LRU hit ratio delta -1.37%\n\nF1 7,500\nLRU hit ratio 32.18%\nTRC hit ratio 34.04%\nDWC hit ratio 32.20%\nDWC - LRU hit ratio delta 0.02%\n\nF1 10,000\nLRU hit ratio 33.27%\nTRC hit ratio 35.57%\nDWC hit ratio 34.66%\nDWC - LRU hit ratio delta 1.39%\n\nF1 12,500\nLRU hit ratio 34.19%\nTRC hit ratio 36.72%\nDWC hit ratio 36.22%\nDWC - LRU hit ratio delta 2.03%\n\nF1 15,000\nLRU hit ratio 34.97%\nTRC hit ratio 37.60%\nDWC hit ratio 37.19%\nDWC - LRU hit ratio delta 2.21%\n\nF1 17,500\nLRU hit ratio 35.62%\nTRC hit ratio 38.32%\nDWC hit ratio 37.87%\nDWC - LRU hit ratio delta 2.24%\n\nF1 20,000\nLRU hit ratio 36.17%\nTRC hit ratio 38.82%\nDWC hit ratio 38.32%\nDWC - LRU hit ratio delta 2.15%\n```\n\n### DS1\n\n<!--\nconst data = {\n  labels: [1e6, 2e6, 3e6, 4e6, 5e6, 6e6, 7e6, 8e6],\n  datasets: [\n    {\n      label: 'Optimal',\n      data: [20.19, 31.79, 41.23, 48.09, 54.96, 61.82, 68.69, 74.93],\n    },\n    {\n      label: 'LRU',\n      data: [3.09, 10.74, 18.59, 20.24, 21.03, 33.95, 38.9, 43.03],\n      borderColor: Utils.color(0),\n    },\n    {\n      label: 'ARC',\n      data: [6.68, 21.99, 24.16, 29.6, 29.44, 36.04, 47.22, 50.89],\n      borderColor: Utils.color(6),\n    },\n    {\n      label: 'DWC',\n      data: [14.05, 27.90, 39.55, 43.45, 49.71, 56.46, 63.21, 69.44],\n      borderColor: Utils.color(2),\n    },\n    {\n      label: 'TrueLRU',\n      data: [10.47, 22.78, 34.45, 39.68, 46.69, 53.64, 61.28, 68.93],\n      borderColor: Utils.color(1),\n    },\n    {\n      label: 'LIRS',\n      data: [12.98, 26.85, 38.02, 38.14, 38.18, 47.25, 59.89, 71.74],\n      borderColor: Utils.color(3),\n    },\n    {\n      label: 'W-TinyLFU',\n      data: [14.79, 28.72, 39.82, 45.26, 51.61, 57.82, 64.22, 70.6],\n      borderColor: Utils.color(8),\n    },\n    {\n      label: 'TinyLFU',\n      data: [14.56, 29.01, 39.58, 45.61, 51.02, 57.76, 64.23, 70.52],\n      borderColor: Utils.color(4),\n    },\n  ]\n};\n-->\n\n![image](https://github.com/falsandtru/dw-cache/assets/3143368/0a7acc4f-73de-4ec5-a2d6-a4b650c1bcda)\n\nW-TinyLFU, (TinyLFU) > DWC > TLRU, (LIRS) > ARC > LRU\n\n```\nDS1 1,000,000\nLRU hit ratio 3.08%\nTRC hit ratio 10.47%\nDWC hit ratio 14.05%\nDWC - LRU hit ratio delta 10.96%\n\nDS1 2,000,000\nLRU hit ratio 10.74%\nTRC hit ratio 22.78%\nDWC hit ratio 27.90%\nDWC - LRU hit ratio delta 17.16%\n\nDS1 3,000,000\nLRU hit ratio 18.59%\nTRC hit ratio 34.45%\nDWC hit ratio 39.55%\nDWC - LRU hit ratio delta 20.96%\n\nDS1 4,000,000\nLRU hit ratio 20.24%\nTRC hit ratio 39.68%\nDWC hit ratio 43.45%\nDWC - LRU hit ratio delta 23.20%\n\nDS1 5,000,000\nLRU hit ratio 21.03%\nTRC hit ratio 46.69%\nDWC hit ratio 49.71%\nDWC - LRU hit ratio delta 28.68%\n\nDS1 6,000,000\nLRU hit ratio 33.95%\nTRC hit ratio 53.64%\nDWC hit ratio 56.46%\nDWC - LRU hit ratio delta 22.50%\n\nDS1 7,000,000\nLRU hit ratio 38.89%\nTRC hit ratio 61.28%\nDWC hit ratio 63.21%\nDWC - LRU hit ratio delta 24.31%\n\nDS1 8,000,000\nLRU hit ratio 43.03%\nTRC hit ratio 68.93%\nDWC hit ratio 69.44%\nDWC - LRU hit ratio delta 26.40%\n```\n\n### S3\n\n<!--\nconst data = {\n  labels: [1e5, 2e5, 3e5, 4e5, 5e5, 6e5, 7e5, 8e5],\n  datasets: [\n    {\n      label: 'Optimal',\n      data: [25.42, 39.79, 50.92, 59.96, 67.09, 72.97, 77.57, 81.27],\n    },\n    {\n      label: 'LRU',\n      data: [2.33, 4.63, 7.59, 12.04, 22.77, 34.63, 46.04, 56.6],\n      borderColor: Utils.color(0),\n    },\n    {\n      label: 'ARC',\n      data: [12.18, 21.74, 27.64, 32, 38.44, 46.25, 52.52, 60.14],\n      borderColor: Utils.color(6),\n    },\n    {\n      label: 'DWC',\n      data: [9.94, 19.39, 28.26, 36.77, 44.50, 52.22, 58.68, 66.02],\n      borderColor: Utils.color(2),\n    },\n    {\n      label: 'TrueLRU',\n      data: [6.99, 15.49, 23.85, 31.94, 40.35, 48.40, 55.86, 63.88],\n      borderColor: Utils.color(1),\n    },\n    {\n      label: 'LIRS',\n      data: [12.4, 15.55, 25.08, 34.69, 44.27, 53.15, 60.99, 67.64],\n      borderColor: Utils.color(3),\n    },\n    {\n      label: 'W-TinyLFU',\n      data: [12.29, 23.55, 33.62, 42.77, 50.96, 58.62, 64.9, 70.26],\n      borderColor: Utils.color(8),\n    },\n    {\n      label: 'TinyLFU',\n      data: [10.46, 22.68, 33.32, 42.91, 51.35, 59.12, 65.25, 70.6],\n      borderColor: Utils.color(4),\n    },\n  ]\n};\n-->\n\n![image](https://github.com/falsandtru/dw-cache/assets/3143368/554fddd2-0686-4ed4-896b-515482955c36)\n\nW-TinyLFU, (TinyLFU) > (LIRS), DWC > TLRU, ARC > LRU\n\n```\nS3 100,000\nLRU hit ratio 2.32%\nTRC hit ratio 6.99%\nDWC hit ratio 9.94%\nDWC - LRU hit ratio delta 7.62%\n\nS3 200,000\nLRU hit ratio 4.63%\nTRC hit ratio 15.49%\nDWC hit ratio 19.39%\nDWC - LRU hit ratio delta 14.76%\n\nS3 300,000\nLRU hit ratio 7.58%\nTRC hit ratio 23.85%\nDWC hit ratio 28.26%\nDWC - LRU hit ratio delta 20.67%\n\nS3 400,000\nLRU hit ratio 12.03%\nTRC hit ratio 31.94%\nDWC hit ratio 36.77%\nDWC - LRU hit ratio delta 24.73%\n\nS3 500,000\nLRU hit ratio 22.76%\nTRC hit ratio 40.35%\nDWC hit ratio 44.50%\nDWC - LRU hit ratio delta 21.74%\n\nS3 600,000\nLRU hit ratio 34.63%\nTRC hit ratio 48.40%\nDWC hit ratio 52.22%\nDWC - LRU hit ratio delta 17.59%\n\nS3 700,000\nLRU hit ratio 46.04%\nTRC hit ratio 55.86%\nDWC hit ratio 58.67%\nDWC - LRU hit ratio delta 12.63%\n\nS3 800,000\nLRU hit ratio 56.59%\nTRC hit ratio 63.88%\nDWC hit ratio 66.02%\nDWC - LRU hit ratio delta 9.42%\n```\n\n### OLTP\n\n<!--\nconst data = {\n  labels: [250, 500, 750, 1000, 1250, 1500, 1750, 2000],\n  datasets: [\n    {\n      label: 'Optimal',\n      data: [38.47, 46.43, 50.67, 53.62, 55.84, 57.62, 59.13, 60.4],\n    },\n    {\n      label: 'LRU',\n      data: [16.47, 23.45, 28.28, 32.83, 36.21, 38.7, 40.79, 42.47],\n      borderColor: Utils.color(0),\n    },\n    {\n      label: 'ARC',\n      data: [21.46, 30.61, 36.04, 39.06, 41.34, 43.15, 44.77, 46.17],\n      borderColor: Utils.color(6),\n    },\n    {\n      label: 'DWC',\n      data: [19.55, 29.48, 34.71, 37.75, 40.07, 41.75, 43.26, 44.59],\n      borderColor: Utils.color(2),\n    },\n    {\n      label: 'TrueLRU',\n      data: [17.06, 27.86, 33.11, 36.53, 38.88, 40.79, 42.36, 43.65],\n      borderColor: Utils.color(1),\n    },\n    {\n      label: 'LIRS',\n      data: [18.27, 26.87, 31.71, 34.82, 37.24, 39.2, 40.79, 42.52],\n      borderColor: Utils.color(3),\n    },\n    {\n      label: 'W-TinyLFU',\n      data: [22.76, 29.21, 32.97, 35.3, 37.52, 38.99, 40.37, 41.67],\n      borderColor: Utils.color(8),\n    },\n    {\n      label: 'TinyLFU',\n      data: [15.9, 19.51, 21.9, 24.41, 26.18, 28.65, 30.03, 31.11],\n      borderColor: Utils.color(4),\n    },\n  ]\n};\n-->\n\n![image](https://github.com/falsandtru/dw-cache/assets/3143368/c898801f-c4b2-4a1e-a03c-58f8b74143c5)\n\nARC > DWC > TLRU > W-TinyLFU > (LIRS) > LRU > (TinyLFU)\n\n```\nOLTP 250\nLRU hit ratio 16.47%\nTRC hit ratio 17.06%\nDWC hit ratio 19.55%\nDWC - LRU hit ratio delta 3.08%\n\nOLTP 500\nLRU hit ratio 23.44%\nTRC hit ratio 27.86%\nDWC hit ratio 29.48%\nDWC - LRU hit ratio delta 6.03%\n\nOLTP 750\nLRU hit ratio 28.28%\nTRC hit ratio 33.11%\nDWC hit ratio 34.71%\nDWC - LRU hit ratio delta 6.43%\n\nOLTP 1,000\nLRU hit ratio 32.83%\nTRC hit ratio 36.53%\nDWC hit ratio 37.75%\nDWC - LRU hit ratio delta 4.92%\n\nOLTP 1,250\nLRU hit ratio 36.20%\nTRC hit ratio 38.88%\nDWC hit ratio 40.07%\nDWC - LRU hit ratio delta 3.86%\n\nOLTP 1,500\nLRU hit ratio 38.69%\nTRC hit ratio 40.79%\nDWC hit ratio 41.75%\nDWC - LRU hit ratio delta 3.06%\n\nOLTP 1,750\nLRU hit ratio 40.78%\nTRC hit ratio 42.36%\nDWC hit ratio 43.26%\nDWC - LRU hit ratio delta 2.47%\n\nOLTP 2,000\nLRU hit ratio 42.46%\nTRC hit ratio 43.65%\nDWC hit ratio 44.59%\nDWC - LRU hit ratio delta 2.12%\n```\n\n### GLI\n\n<!--\nconst data = {\n  labels: [250, 500, 750, 1000, 1250, 1500, 1750, 2000],\n  datasets: [\n    {\n      label: 'Optimal',\n      data: [17.71,34.33, 46.13, 53.15, 57.31, 57.96, 57.96, 57.96],\n    },\n    {\n      label: 'LRU',\n      data: [0.91, 0.95, 1.15, 11.21, 21.25, 36.56, 45.04, 57.41],\n      borderColor: Utils.color(0),\n    },\n    {\n      label: 'ARC',\n      data: [1.38, 1.38, 1.41, 21.3, 34.43, 50.44, 55.06, 57.41],\n      borderColor: Utils.color(6),\n    },\n    {\n      label: 'DWC',\n      data: [15.82, 31.38, 41.65, 47.87, 52.54, 53.64, 54.77, 57.96],\n      borderColor: Utils.color(2),\n    },\n    {\n      label: 'TrueLRU',\n      data: [10.62, 25.03, 37.28, 47.17, 52.04, 53.00, 55.88, 57.96],\n      borderColor: Utils.color(1),\n    },\n    {\n      label: 'LIRS',\n      data: [15.91, 33.6, 43.61, 50.56, 51.85, 53.55, 55.58, 57.96],\n      borderColor: Utils.color(3),\n    },\n    {\n      label: 'W-TinyLFU',\n      data: [15.15, 33.08, 43.11, 50.57, 51.87, 53.57, 55.61, 57.96],\n      borderColor: Utils.color(8),\n    },\n    {\n      label: 'TinyLFU',\n      data: [16.56, 33.85, 43.86, 50.96, 52.05, 53.57, 55.89, 57.96],\n      borderColor: Utils.color(4),\n    },\n  ]\n};\n-->\n\n![image](https://github.com/falsandtru/dw-cache/assets/3143368/8d788c8b-166f-4098-a3d7-22e404848a8a)\n\nW-TinyLFU, (TinyLFU), (LIRS) > DWC > TLRU >> ARC > LRU\n\n```\nGLI 250\nLRU hit ratio 0.93%\nTRC hit ratio 10.62%\nDWC hit ratio 15.82%\nDWC - LRU hit ratio delta 14.89%\n\nGLI 500\nLRU hit ratio 0.96%\nTRC hit ratio 25.03%\nDWC hit ratio 31.38%\nDWC - LRU hit ratio delta 30.41%\n\nGLI 750\nLRU hit ratio 1.16%\nTRC hit ratio 37.28%\nDWC hit ratio 41.65%\nDWC - LRU hit ratio delta 40.49%\n\nGLI 1,000\nLRU hit ratio 11.22%\nTRC hit ratio 47.17%\nDWC hit ratio 47.87%\nDWC - LRU hit ratio delta 36.65%\n\nGLI 1,250\nLRU hit ratio 21.25%\nTRC hit ratio 52.04%\nDWC hit ratio 52.54%\nDWC - LRU hit ratio delta 31.28%\n\nGLI 1,500\nLRU hit ratio 36.56%\nTRC hit ratio 53.00%\nDWC hit ratio 53.64%\nDWC - LRU hit ratio delta 17.07%\n\nGLI 1,750\nLRU hit ratio 45.04%\nTRC hit ratio 55.88%\nDWC hit ratio 54.77%\nDWC - LRU hit ratio delta 9.72%\n\nGLI 2,000\nLRU hit ratio 57.41%\nTRC hit ratio 57.96%\nDWC hit ratio 57.96%\nDWC - LRU hit ratio delta 0.54%\n```\n\n<!--\nLOOP 100\nLRU hit ratio 0.00%\nTRC hit ratio 0.00%\nDWC hit ratio 8.12%\nDWC - LRU hit ratio delta 8.12%\n\nLOOP 250\nLRU hit ratio 0.00%\nTRC hit ratio 0.00%\nDWC hit ratio 21.85%\nDWC - LRU hit ratio delta 21.85%\n\nLOOP 500\nLRU hit ratio 0.00%\nTRC hit ratio 0.00%\nDWC hit ratio 43.58%\nDWC - LRU hit ratio delta 43.58%\n\nLOOP 750\nLRU hit ratio 0.00%\nTRC hit ratio 0.00%\nDWC hit ratio 67.48%\nDWC - LRU hit ratio delta 67.48%\n\nLOOP 1,000\nLRU hit ratio 0.00%\nTRC hit ratio 0.00%\nDWC hit ratio 98.10%\nDWC - LRU hit ratio delta 98.10%\n\nLOOP 1,250\nLRU hit ratio 99.80%\nTRC hit ratio 99.80%\nDWC hit ratio 99.80%\nDWC - LRU hit ratio delta 0.00%\n-->\n\n## Throughput\n\n- Clock: spica/clock\n- ILRU: lru-cache (https://www.npmjs.com/package/lru-cache)\n- LRU: spica/lru\n- TRC-C: spica/tlru (spica/tlru.clock)\n- TRC-L: spica/tlru.lru\n- DWC: spica/cache\n\nhttps://github.com/falsandtru/spica/blob/master/benchmark/cache.ts\n\n```\n    OS: Linux 6.2 Ubuntu 22.04.4 LTS 22.04.4 LTS (Jammy Jellyfish)\n    CPU: (4) x64 AMD EPYC 7763 64-Core Processor\n    Memory: 14.61 GB / 15.61 GB\n    Container: Yes\n\n'Clock  new x 1,580,578 ops/sec ±2.36% (120 runs sampled)'\n\n'TClock new x 1,635,917 ops/sec ±1.73% (114 runs sampled)'\n\n'ILRU   new x 17,306 ops/sec ±0.72% (122 runs sampled)'\n\n'LRU    new x 26,446,766 ops/sec ±1.27% (120 runs sampled)'\n\n'TLRU-C new x 25,447,708 ops/sec ±1.16% (120 runs sampled)'\n\n'TLRU-L new x 25,516,873 ops/sec ±1.15% (120 runs sampled)'\n\n'DWC    new x 8,852,793 ops/sec ±0.48% (123 runs sampled)'\n\n'Clock  simulation 100 10% x 9,916,253 ops/sec ±0.82% (121 runs sampled)'\n\n'TClock simulation 100 10% x 9,178,812 ops/sec ±0.41% (122 runs sampled)'\n\n'ILRU   simulation 100 10% x 8,795,920 ops/sec ±0.45% (121 runs sampled)'\n\n'LRU    simulation 100 10% x 11,042,280 ops/sec ±0.41% (122 runs sampled)'\n\n'TLRU-C simulation 100 10% x 10,776,622 ops/sec ±0.69% (122 runs sampled)'\n\n'TLRU-L simulation 100 10% x 9,087,601 ops/sec ±0.55% (122 runs sampled)'\n\n'DWC    simulation 100 10% x 5,970,465 ops/sec ±0.31% (122 runs sampled)'\n\n'Clock  simulation 1,000 10% x 9,957,449 ops/sec ±0.44% (123 runs sampled)'\n\n'TClock simulation 1,000 10% x 9,045,578 ops/sec ±0.87% (122 runs sampled)'\n\n'ILRU   simulation 1,000 10% x 8,120,270 ops/sec ±0.40% (123 runs sampled)'\n\n'LRU    simulation 1,000 10% x 10,033,399 ops/sec ±1.03% (121 runs sampled)'\n\n'TLRU-C simulation 1,000 10% x 10,012,036 ops/sec ±0.48% (123 runs sampled)'\n\n'TLRU-L simulation 1,000 10% x 8,728,394 ops/sec ±0.53% (123 runs sampled)'\n\n'DWC    simulation 1,000 10% x 6,824,871 ops/sec ±0.44% (121 runs sampled)'\n\n'Clock  simulation 10,000 10% x 8,950,040 ops/sec ±0.68% (122 runs sampled)'\n\n'TClock simulation 10,000 10% x 8,184,728 ops/sec ±0.36% (123 runs sampled)'\n\n'ILRU   simulation 10,000 10% x 6,836,598 ops/sec ±0.35% (121 runs sampled)'\n\n'LRU    simulation 10,000 10% x 8,375,776 ops/sec ±0.40% (121 runs sampled)'\n\n'TLRU-C simulation 10,000 10% x 8,056,049 ops/sec ±0.87% (120 runs sampled)'\n\n'TLRU-L simulation 10,000 10% x 7,152,724 ops/sec ±0.30% (123 runs sampled)'\n\n'DWC    simulation 10,000 10% x 5,707,307 ops/sec ±0.40% (122 runs sampled)'\n\n'Clock  simulation 100,000 10% x 6,066,442 ops/sec ±1.54% (120 runs sampled)'\n\n'TClock simulation 100,000 10% x 5,931,329 ops/sec ±1.52% (118 runs sampled)'\n\n'ILRU   simulation 100,000 10% x 3,989,516 ops/sec ±1.24% (117 runs sampled)'\n\n'LRU    simulation 100,000 10% x 5,775,982 ops/sec ±1.73% (119 runs sampled)'\n\n'TLRU-C simulation 100,000 10% x 6,121,879 ops/sec ±2.03% (117 runs sampled)'\n\n'TLRU-L simulation 100,000 10% x 5,372,740 ops/sec ±2.16% (117 runs sampled)'\n\n'DWC    simulation 100,000 10% x 4,371,865 ops/sec ±1.97% (114 runs sampled)'\n\n'Clock  simulation 1,000,000 10% x 2,921,542 ops/sec ±2.82% (107 runs sampled)'\n\n'TClock simulation 1,000,000 10% x 2,734,509 ops/sec ±4.05% (102 runs sampled)'\n\n'ILRU   simulation 1,000,000 10% x 1,702,357 ops/sec ±2.64% (108 runs sampled)'\n\n'LRU    simulation 1,000,000 10% x 2,404,423 ops/sec ±3.55% (107 runs sampled)'\n\n'TLRU-C simulation 1,000,000 10% x 2,509,557 ops/sec ±3.64% (106 runs sampled)'\n\n'TLRU-L simulation 1,000,000 10% x 2,400,923 ops/sec ±3.88% (103 runs sampled)'\n\n'DWC    simulation 1,000,000 10% x 3,086,653 ops/sec ±3.95% (107 runs sampled)'\n\n'Clock  simulation 100 50% x 11,638,221 ops/sec ±0.44% (123 runs sampled)'\n\n'TClock simulation 100 50% x 10,645,049 ops/sec ±0.69% (123 runs sampled)'\n\n'ILRU   simulation 100 50% x 10,786,602 ops/sec ±0.47% (122 runs sampled)'\n\n'LRU    simulation 100 50% x 12,558,754 ops/sec ±0.62% (121 runs sampled)'\n\n'TLRU-C simulation 100 50% x 12,613,469 ops/sec ±0.48% (122 runs sampled)'\n\n'TLRU-L simulation 100 50% x 10,785,803 ops/sec ±0.45% (122 runs sampled)'\n\n'DWC    simulation 100 50% x 6,507,728 ops/sec ±0.43% (123 runs sampled)'\n\n'Clock  simulation 1,000 50% x 11,225,959 ops/sec ±0.41% (122 runs sampled)'\n\n'TClock simulation 1,000 50% x 10,633,288 ops/sec ±0.51% (123 runs sampled)'\n\n'ILRU   simulation 1,000 50% x 9,807,774 ops/sec ±0.83% (122 runs sampled)'\n\n'LRU    simulation 1,000 50% x 11,547,226 ops/sec ±0.47% (122 runs sampled)'\n\n'TLRU-C simulation 1,000 50% x 11,500,223 ops/sec ±0.69% (121 runs sampled)'\n\n'TLRU-L simulation 1,000 50% x 10,370,843 ops/sec ±0.40% (123 runs sampled)'\n\n'DWC    simulation 1,000 50% x 5,861,780 ops/sec ±0.37% (123 runs sampled)'\n\n'Clock  simulation 10,000 50% x 10,005,777 ops/sec ±0.58% (122 runs sampled)'\n\n'TClock simulation 10,000 50% x 9,164,085 ops/sec ±0.44% (122 runs sampled)'\n\n'ILRU   simulation 10,000 50% x 8,145,309 ops/sec ±0.44% (121 runs sampled)'\n\n'LRU    simulation 10,000 50% x 8,836,874 ops/sec ±0.51% (120 runs sampled)'\n\n'TLRU-C simulation 10,000 50% x 8,739,594 ops/sec ±0.53% (122 runs sampled)'\n\n'TLRU-L simulation 10,000 50% x 7,752,474 ops/sec ±0.44% (121 runs sampled)'\n\n'DWC    simulation 10,000 50% x 4,774,496 ops/sec ±0.49% (120 runs sampled)'\n\n'Clock  simulation 100,000 50% x 6,886,961 ops/sec ±1.39% (118 runs sampled)'\n\n'TClock simulation 100,000 50% x 6,671,489 ops/sec ±1.43% (118 runs sampled)'\n\n'ILRU   simulation 100,000 50% x 4,727,141 ops/sec ±1.40% (117 runs sampled)'\n\n'LRU    simulation 100,000 50% x 6,267,110 ops/sec ±2.01% (117 runs sampled)'\n\n'TLRU-C simulation 100,000 50% x 6,497,513 ops/sec ±1.95% (118 runs sampled)'\n\n'TLRU-L simulation 100,000 50% x 5,929,699 ops/sec ±2.30% (117 runs sampled)'\n\n'DWC    simulation 100,000 50% x 4,007,906 ops/sec ±1.48% (110 runs sampled)'\n\n'Clock  simulation 1,000,000 50% x 3,388,591 ops/sec ±3.09% (105 runs sampled)'\n\n'TClock simulation 1,000,000 50% x 3,030,444 ops/sec ±3.52% (103 runs sampled)'\n\n'ILRU   simulation 1,000,000 50% x 1,957,735 ops/sec ±3.24% (106 runs sampled)'\n\n'LRU    simulation 1,000,000 50% x 2,378,468 ops/sec ±3.26% (107 runs sampled)'\n\n'TLRU-C simulation 1,000,000 50% x 2,319,526 ops/sec ±3.01% (110 runs sampled)'\n\n'TLRU-L simulation 1,000,000 50% x 2,326,281 ops/sec ±2.40% (107 runs sampled)'\n\n'DWC    simulation 1,000,000 50% x 1,873,066 ops/sec ±3.42% (101 runs sampled)'\n\n'Clock  simulation 100 90% x 17,142,365 ops/sec ±0.70% (122 runs sampled)'\n\n'TClock simulation 100 90% x 17,515,002 ops/sec ±0.92% (120 runs sampled)'\n\n'ILRU   simulation 100 90% x 16,941,103 ops/sec ±0.74% (121 runs sampled)'\n\n'LRU    simulation 100 90% x 16,965,079 ops/sec ±0.89% (120 runs sampled)'\n\n'TLRU-C simulation 100 90% x 16,764,673 ops/sec ±0.80% (119 runs sampled)'\n\n'TLRU-L simulation 100 90% x 15,833,669 ops/sec ±0.67% (122 runs sampled)'\n\n'DWC    simulation 100 90% x 8,241,562 ops/sec ±0.33% (122 runs sampled)'\n\n'Clock  simulation 1,000 90% x 16,186,628 ops/sec ±0.92% (122 runs sampled)'\n\n'TClock simulation 1,000 90% x 16,620,457 ops/sec ±0.68% (122 runs sampled)'\n\n'ILRU   simulation 1,000 90% x 14,897,888 ops/sec ±0.62% (122 runs sampled)'\n\n'LRU    simulation 1,000 90% x 15,072,880 ops/sec ±0.62% (122 runs sampled)'\n\n'TLRU-C simulation 1,000 90% x 14,802,277 ops/sec ±1.06% (120 runs sampled)'\n\n'TLRU-L simulation 1,000 90% x 14,243,896 ops/sec ±0.60% (122 runs sampled)'\n\n'DWC    simulation 1,000 90% x 7,878,478 ops/sec ±0.55% (123 runs sampled)'\n\n'Clock  simulation 10,000 90% x 14,397,140 ops/sec ±0.96% (122 runs sampled)'\n\n'TClock simulation 10,000 90% x 14,674,408 ops/sec ±0.76% (122 runs sampled)'\n\n'ILRU   simulation 10,000 90% x 12,163,240 ops/sec ±0.56% (122 runs sampled)'\n\n'LRU    simulation 10,000 90% x 11,176,342 ops/sec ±1.02% (121 runs sampled)'\n\n'TLRU-C simulation 10,000 90% x 10,623,051 ops/sec ±0.62% (120 runs sampled)'\n\n'TLRU-L simulation 10,000 90% x 10,157,939 ops/sec ±0.90% (122 runs sampled)'\n\n'DWC    simulation 10,000 90% x 7,044,033 ops/sec ±0.74% (122 runs sampled)'\n\n'Clock  simulation 100,000 90% x 9,289,594 ops/sec ±1.22% (117 runs sampled)'\n\n'TClock simulation 100,000 90% x 9,424,672 ops/sec ±1.28% (117 runs sampled)'\n\n'ILRU   simulation 100,000 90% x 7,244,655 ops/sec ±0.98% (117 runs sampled)'\n\n'LRU    simulation 100,000 90% x 7,412,012 ops/sec ±2.06% (115 runs sampled)'\n\n'TLRU-C simulation 100,000 90% x 7,348,881 ops/sec ±2.79% (113 runs sampled)'\n\n'TLRU-L simulation 100,000 90% x 7,138,284 ops/sec ±1.86% (113 runs sampled)'\n\n'DWC    simulation 100,000 90% x 5,590,257 ops/sec ±1.48% (116 runs sampled)'\n\n'Clock  simulation 1,000,000 90% x 5,098,637 ops/sec ±3.30% (103 runs sampled)'\n\n'TClock simulation 1,000,000 90% x 4,743,456 ops/sec ±3.51% (103 runs sampled)'\n\n'ILRU   simulation 1,000,000 90% x 3,168,501 ops/sec ±2.45% (111 runs sampled)'\n\n'LRU    simulation 1,000,000 90% x 2,594,390 ops/sec ±3.09% (112 runs sampled)'\n\n'TLRU-C simulation 1,000,000 90% x 2,546,277 ops/sec ±2.43% (109 runs sampled)'\n\n'TLRU-L simulation 1,000,000 90% x 2,478,672 ops/sec ±2.63% (111 runs sampled)'\n\n'DWC    simulation 1,000,000 90% x 2,154,161 ops/sec ±1.80% (114 runs sampled)'\n\n'ILRU   simulation 100 90% expire x 4,875,225 ops/sec ±2.21% (119 runs sampled)'\n\n'DWC    simulation 100 90% expire x 7,322,013 ops/sec ±0.68% (120 runs sampled)'\n\n'ILRU   simulation 1,000 90% expire x 4,600,040 ops/sec ±2.52% (118 runs sampled)'\n\n'DWC    simulation 1,000 90% expire x 7,126,746 ops/sec ±0.67% (122 runs sampled)'\n\n'ILRU   simulation 10,000 90% expire x 3,992,238 ops/sec ±2.12% (119 runs sampled)'\n\n'DWC    simulation 10,000 90% expire x 5,431,828 ops/sec ±0.87% (120 runs sampled)'\n\n'ILRU   simulation 100,000 90% expire x 3,132,253 ops/sec ±2.06% (114 runs sampled)'\n\n'DWC    simulation 100,000 90% expire x 2,914,127 ops/sec ±2.99% (100 runs sampled)'\n\n'ILRU   simulation 1,000,000 90% expire x 1,361,462 ops/sec ±1.48% (114 runs sampled)'\n\n'DWC    simulation 1,000,000 90% expire x 1,349,727 ops/sec ±2.02% (111 runs sampled)'\n```\n\n## API\n\n```ts\nexport namespace Cache {\n  export interface Options<K, V = undefined> {\n    // Max entries.\n    // Range: 1-\n    readonly capacity?: number;\n    // Max costs.\n    // Range: L-\n    readonly resource?: number;\n    readonly age?: number;\n    readonly eagerExpiration?: boolean;\n    // WARNING: Don't add any new key in disposing.\n    readonly disposer?: (value: V, key: K) => void;\n    readonly capture?: {\n      readonly delete?: boolean;\n      readonly clear?: boolean;\n    };\n    // Mainly for experiments.\n    // Min LRU ratio.\n    // Range: 0-100\n    readonly window?: number;\n    // Sample ratio of LRU in LFU.\n    // Range: 0-100\n    readonly sample?: number;\n    readonly sweep?: {\n      readonly threshold?: number;\n      readonly window?: number;\n      readonly room?: number;\n      readonly ground?: number;\n      readonly interval?: number;\n      readonly slide?: number;\n    };\n  }\n}\nexport class Cache<K, V> {\n  constructor(capacity: number, sweep?: boolean);\n  constructor(capacity: number, opts?: Cache.Options<K, V>);\n  constructor(opts: Cache.Options<K, V>);\n  readonly length: number;\n  readonly size: number;\n  add(key: K, value: V, opts?: { size?: number; age?: number; }): boolean;\n  add(this: Cache<K, undefined>, key: K, value?: V, opts?: { size?: number; age?: number; }): boolean;\n  put(key: K, value: V, opts?: { size?: number; age?: number; }): boolean;\n  put(this: Cache<K, undefined>, key: K, value?: V, opts?: { size?: number; age?: number; }): boolean;\n  set(key: K, value: V, opts?: { size?: number; age?: number; }): this;\n  set(this: Cache<K, undefined>, key: K, value?: V, opts?: { size?: number; age?: number; }): this;\n  get(key: K): V | undefined;\n  has(key: K): boolean;\n  delete(key: K): boolean;\n  clear(): void;\n  resize(capacity: number, resource?: number): void;\n  [Symbol.iterator](): Iterator<[K, V], undefined, undefined>;\n}\n```\n","readmeFilename":"README.md"}