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Node](#usage-from-node)\n- [Parser](#parser)\n  - [Format of an HDL file](#format-of-an-hdl-file)\n  - [Parsing a file to AST](#parsing-a-file-to-ast)\n  - [AST nodes specification](#ast-nodes-specification)\n- [Emulator](#emulator)\n  - [Online tool](#online-tool)\n  - [Built-in gates](#built-in-gates)\n  - [Viewing gate specification](#viewing-gate-specification)\n  - [Specifying output format](#specifying-output-format)\n  - [Columns whitelist](#columns-whitelist)\n  - [Testing gates on passed data](#testing-gates-on-passed-data)\n  - [Pins](#pins)\n    - [Pin size and ranges](#pin-size-and-ranges)\n    - [Pin events](#pin-events)\n    - [Connecting pins together](#connecting-pins-together)\n  - [Creating gates from default spec](#creating-gates-from-default-spec)\n  - [Exec on set of data](#exec-on-set-of-data)\n  - [Validating passed data on gate logic](#validating-passed-data-on-gate-logic)\n  - [Data files for execution](#data-files-for-execution)\n  - [Gates scripting](#gates-scripting)\n    - [Executing scripts](#executing-scripts)\n    - [Script controller commands](#script-controller-commands)\n    - [Script emulator commands](#script-emulator-commands)\n  - [Sequential run](#sequential-run)\n  - [Gate events](#gate-events)\n  - [Main chip groups](#main-chip-groups)\n    - [Very basic chips](#very-basic-chips)\n    - [Basic chips](#basic-chips)\n    - [ALU](#alu)\n    - [Memory chips](#memory-chips)\n    - [Interface chips](#interface-chips)\n      - [Screen](#screen)\n      - [Keyboard](#keyboard)\n  - [Clock](#clock)\n    - [Clock events](#clock-events)\n    - [Clock rate](#clock-rate)\n  - [Composite gates](#composite-gates)\n    - [Building chips in HDL](#building-chips-in-hdl)\n    - [Viewing composite gate specification](#viewing-composite-gate-specification)\n    - [Using custom and built-in gates in implementation](#using-custom-and-built-in-gates-in-implementation)\n    - [Loading HDL chips from Node](#loading-hdl-chips-from-node)\n- [Code generator](#code-generator)\n  - [Exporting from AST](#exporting-from-ast)\n  - [Exporting from composite gates](#exporting-from-composite-gates)\n\n## Installation\n\nThe `hdl-js` tool can be installed as an [npm module](https://www.npmjs.com/package/hdl-js):\n\n```\nnpm install -g hdl-js\n\nhdl-js --help\n```\n\n## Development\n\n1. Fork https://github.com/DmitrySoshnikov/hdl-js repo\n2. If there is an actual issue from the [issues](https://github.com/DmitrySoshnikov/hdl-js/issues) list you'd like to work on, feel free to assign it yourself, or comment on it to avoid collisions (open a new issue if needed)\n3. Make your changes\n4. Make sure `npm test` still passes (add new tests if needed)\n5. Submit a PR\n\nFor development from the github repository, run build command to generate the parser module, and transpile JS code:\n\n```\ngit clone https://github.com/<your-github-account>/hdl-js.git\ncd hdl-js\nnpm install\nnpm run build\n\n./bin/hdl-js --help\n```\n\n> **NOTE:** JS code transpilation is used to support older versions of Node. For faster development cycle you can use npm run watch command, which continuously transpiles JS code.\n\n## Usage as a CLI\n\nCheck the options available from CLI:\n\n```\nhdl-js --help\n```\n\n```\nUsage: hdl-js [options]\n\nOptions:\n  --help, -h          Show help                                        [boolean]\n  --version, -v       Show version number                              [boolean]\n  --gate, -g          Name of a built-in gate or path to an HDL file\n  --parse, -p         Parse the HDL file, and print AST\n  --list, -l          List supported built-in gates\n  --describe, -d      Prints gate's specification\n  --exec-on-data, -e  Evaluates gate's logic on passed data; validates outputs\n                      if passed\n  --format, -f        Values format (binary, hexadecimal, decimal)\n                                                  [choices: \"bin\", \"hex\", \"dec\"]\n  --run, -r           Runs sequentially the rows from --exec-on-data table\n  --clock-rate        Rate (number of cycles per second) for the System clock\n  --columns, -c       Whitelist of columns (comma-separated) to show in the\n                      table\n  --script, -s        Run testing script, which automatically loads a gate,\n                      tests the logic, and compares the results.\n```\n\n> **NOTE:** the implementation of some built-in chips, and the HDL format is heavily inspired by the wonderful [nand2tetris](http://nand2tetris.org/) course by Noam Nisan and Shimon Schocken.\n\nExample of a CLI command to describe `Xor` gate:\n\n```\nhdl-js --gate Xor --describe\n\n\"Xor\" gate:\n\nDescription:\n\n  Implements bitwise 1-bit Xor ^ operation.\n\n...\n```\n\n### Usage from Node\n\nThe tool can also be used as a Node module:\n\n```js\nconst hdl = require('hdl-js');\n\n// Check the API:\nconsole.log(hdl);\n```\n\nThe `hdl-js` exposes the following API:\n\n- `parse(hdl: string)` -- parses an HDL code; convenient facade method for `parser.parse`\n- `parseFile(fileName: string)` -- parses an HDL file; facade for `parser.parseFile`\n- `fromHDLFile(fileName: string)` -- loads a gate class defined in an HDL file; facade for `HDLClassFactory.fromHDLFile`\n- `fromHDL(hdl: string)` -- creates a gate class according to passed HDL spec; facade for `HDLClassFactory.fromHDL`\n- [parser](#parser) -- the parser module exposed\n- [emulator](#emulator) -- hardware emulator, which includes:\n  - `Pin` - a pin \"wire\" used to patch inputs and outputs of a gate\n  - `BuiltInGate` -- base class for all built-in gates\n  - `CompositeGate` -- base class used for user-defined gates from HDL; see [Composite gates](#composite-gates) section\n  - `HDLClassFactory` -- class loader for gates defined in HDL\n  - [ScriptInterpreter](#gates-scripting) -- execution engine for test scripts\n  - [Clock](#clock) -- class to manage clocked gates. Contains:\n    - `SystemClock` -- main System clock used to synchronize all gated chips\n  - `BuiltInGates` -- map of all [built-in gates](#built-in-gates):\n    - `And`\n    - `Or`\n    - ...\n- `generateFromAST(ast)` -- generates an HDL code from AST; convenient facade for `generator.fromAST`\n- `generateFromCompositeGate(gate)` -- generates an HDL code from a composite gate instance; convenient facade for `generator.fromCompositeGate`\n- [generator](#code-generator) -- the generator module exposed\n\n\n## Parser\n\nThe `hdl-js` is implemented as an automatic LR parser using [Syntax](https://www.npmjs.com/package/syntax-cli) tool. The parser module is generated from the corresponding [grammar](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/parser/hdl.g) file.\n\n### Format of an HDL file\n\nA hardware chip is described via the `CHIP` declaration, followed by a _chip name_, and a set of _sections_:\n\n```\nCHIP <chip-name> {\n  <section>\n  <section>\n  ...\n}\n```\n\nThe [sections](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/parser/hdl.g#L121-L127) include:\n\n- `IN` -- inputs of a gate\n- `OUT` -- outputs of a gate\n- `PARTS` -- the actual implementation _body_ of a chip, composed from other chips\n- `BUILTIN` -- refer to a name of a built-in chip: in this case the implementation is fully take from the built-in gate, and the `PARTS` section can be omitted\n- `CLOCKED` -- describes which inputs/outputs are [clocked](#clock)\n\nLet's take a look at the [examples/And.hdl](https://github.com/DmitrySoshnikov/hdl-js/blob/master/examples/And.hdl) file:\n\n```\n/**\n * And gate:\n * out = 1 if (a == 1 and b == 1)\n *       0 otherwise\n */\n\nCHIP And {\n  IN a, b;\n  OUT out;\n\n  PARTS:\n\n  Nand(a=a, b=b, out=n);\n  Nand(a=n, b=n, out=out);\n}\n```\n\nOnce we have an HDL file, we can feed it to the parser, and get its AST.\n\n### Parsing a file to AST\n\nThe parser can be used from CLI, and from Node.\n\nTaking the [examples/And.hdl](https://github.com/DmitrySoshnikov/hdl-js/blob/master/examples/And.hdl) file from above, and running the:\n\n```\n./bin/hdl-js --gate examples/And.hdl --parse\n```\n\nWe get the following AST (abstract syntax tree):\n\n```js\n{\n  type: 'Chip',\n  name: 'And',\n  inputs: [\n    {\n      type: 'Name',\n      value: 'a'\n    },\n    {\n      type: 'Name',\n      value: 'b'\n    }\n  ],\n  outputs: [\n    {\n      type: 'Name',\n      value: 'out'\n    }\n  ],\n  parts: [\n    {\n      type: 'ChipCall',\n      name: 'Nand',\n      arguments: [\n        {\n          type: 'Argument',\n          name: {\n            type: 'Name',\n            value: 'a'\n          },\n          value: {\n            type: 'Name',\n            value: 'a'\n          }\n        },\n        {\n          type: 'Argument',\n          name: {\n            type: 'Name',\n            value: 'b'\n          },\n          value: {\n            type: 'Name',\n            value: 'b'\n          }\n        },\n        {\n          type: 'Argument',\n          name: {\n            type: 'Name',\n            value: 'out'\n          },\n          value: {\n            type: 'Name',\n            value: 'n'\n          }\n        }\n      ]\n    },\n    {\n      type: 'ChipCall',\n      name: 'Nand',\n      arguments: [\n        {\n          type: 'Argument',\n          name: {\n            type: 'Name',\n            value: 'a'\n          },\n          value: {\n            type: 'Name',\n            value: 'n'\n          }\n        },\n        {\n          type: 'Argument',\n          name: {\n            type: 'Name',\n            value: 'b'\n          },\n          value: {\n            type: 'Name',\n            value: 'n'\n          }\n        },\n        {\n          type: 'Argument',\n          name: {\n            type: 'Name',\n            value: 'out'\n          },\n          value: {\n            type: 'Name',\n            value: 'out'\n          }\n        }\n      ]\n    }\n  ],\n  builtins: [],\n  clocked: [],\n}\n```\n\nThe `parse` command is also available from Node:\n\n```js\nconst fs = require('fs');\nconst hdl = require('hdl-js');\n\nconst hdlCode = fs.readFileSync('./examples/And.hdl', 'utf-8');\n\nconsole.log(hdl.parse(hdlCode)); // HDL AST\n```\n\nThere is also convenient `parseFile` method:\n\n```js\nconst hdl = require('hdl-js');\n\nconsole.log(hdl.parseFile('./examples/And.hdl')); // AST\n```\n\n### AST nodes specification\n\nThe AST format of the HDL is currently simple, and includes the following node types:\n\n#### `Chip` AST node\n\nThis is the top-level `\"Chip\"` node, and has the following properties:\n\n```js\n{\n  type: 'Chip',\n\n  /**\n   * List of inputs pins.\n   */\n  inputs: [Name, ...],\n\n  /**\n   * List of output pins.\n   */\n  outputs: [Name, ...],\n\n  /**\n   * Gate implementation list.\n   */\n  parts: [ChipCall, ...],\n\n  /**\n   * If present, contains the names of the built-in chips used in this gate.\n   */\n  builtins: [Name, ...],\n\n  /**\n   * If present, shows the list of clocked inputs/outputs.\n   */\n  clocked: [Name, ...],\n}\n```\n\n#### `Name` AST node\n\nThe `Name` type is used to define the names of the input/output pins, names of the arguments in [ChipCall](#chipcall-ast-node), etc. The node has the following properties:\n\n```js\n{\n  type: 'Name',\n\n  /*\n   * The actual name of a pin.\n   *\n   * Example: `IN a;`, the `value` is `a`.\n   */\n  value: string,\n\n  /**\n   * The `size` is only available in the input/output names.\n   *\n   * Example: `IN a[16];`, the `size` is 16.\n   */\n  size?: number,\n\n  /**\n   * An index of a particular bit. The `index` property is\n   * only available in the arguments of a `ChipCall`.\n   *\n   * Example: `And(a=a[4], ...)`, the `index` is 4 here.\n   */\n  index?: number,\n\n  /**\n   * A range of the bits. The `range` property is\n   * only available in arguments of a `ChipCall`/\n   *\n   * Example: `Mux4Way16(..., sel=address[0..11])`,\n   * the range (inclusive) here is `0..11`.\n   */\n  range?: {\n    from: number,\n    to: number,\n  },\n}\n```\n\n#### `ChipCall` AST node\n\nThe `ChipCall` can appear only in the `parts` section of the `'Chip'` node. This is an evaluation call to an internal chip, used in implementation of this gate.\n\nIt has the following properties:\n\n```js\n{\n  type: 'ChipCall',\n\n  /**\n   * The name of the internal chip, which is being called.\n   */\n  name: string,\n\n  /**\n   * The list of arguments to the call. The values in each argument\n   * correspond to the inputs/outputs specification of a gate.\n   */\n  arguments: [Argument, ...]\n}\n```\n\n#### `Argument` AST node\n\nArguments appear as parts of the [ChipCall](#chipcall-ast-node) node types. An argument has the following properties:\n\n```js\n{\n  type: 'Argument',\n\n  /**\n   * The name of the argument.\n   */\n  name: Name,\n\n  /**\n   * The value of the argument.\n   */\n  value: Constant | Name,\n}\n```\n\n#### `Constant` AST node\n\nConstants can be used as _input_ values for pins. These are _numbers_, and two special names, `false`, and `true`, which correspond respectively to `0`, and `1` values.\n\n```js\n{\n  type: 'Constant',\n\n  /**\n   * The number value of the constant.\n   */\n  value: NUMBER,\n\n  /**\n   * The value as it appears in the source code.\n   */\n  raw: 'true' | 'false' | NUMBER\n}\n```\n\n## Emulator\n\n[Hardware emulator](https://github.com/DmitrySoshnikov/hdl-js/tree/master/src/emulator/hardware) module simulates and tests logic gates and chips implemented in the HDL, and also provides canonical implementation of the [built-in chips](https://github.com/DmitrySoshnikov/hdl-js/tree/master/src/emulator/hardware/builtin-gates).\n\n### Online tool\n\nThe emulator module is exposed as a UI tool, where you can design chips in HDL, introspect built-in gates, and check the results of gates evaluation.\n\n<a href=\"http://dmitrysoshnikov.com/hdl-hardware-simulator/\" target=\"_blank\">Try it out here!</a>\n\n<p align=\"center\">\n  <img src=\"http://dmitrysoshnikov.com/wp-content/uploads/2018/03/hdl-hardward-simulator-screen-1024x518.png\" alt=\"Hardware simulator UI tool\" />\n<p/>\n\n### Built-in gates\n\nIn general, all the gates can be built [manually in HDL](#composite-gates) from the very basic `Nand` or `Nor` gates. However, `hdl-js` also provides implementation of most of the computer chips, built directly in JavaScript.\n\nYou can use these gates as building blocks with a guaranteed faster implementation, and also to check your own implementation, in case you build a custom version of a particular basic chip.\n\nThe `--list` (`-l`) command shows all the _built-in gates_ available in the emulator. The gates can be analyzed, executed, and used further as basic building blocks in construction of [compound gates](#composite-gates).\n\n```\n./bin/hdl-js --list\n\nBuilt-in gates:\n\n- And\n- And16\n- Or\n- ...\n```\n\nOnce you know a gate of interest, you can introspect its specification.\n\n### Viewing gate specification\n\nTo see the specification of a particular gate, we can use `--describe` (`-d`) option, passing the name of a needed `--gate` (`-g`):\n\n```\n./bin/hdl-js --gate And --describe\n```\n\nResult:\n\n```\n\"And\" gate:\n\nDescription:\n\n  Implements bitwise 1-bit And & operation.\n\nInputs:\n\n  - a\n  - b\n\nOutputs:\n\n  - out\n\nTruth table:\n\n┌───┬───┬─────┐\n│ a │ b │ out │\n├───┼───┼─────┤\n│ 0 │ 0 │  0  │\n├───┼───┼─────┤\n│ 0 │ 1 │  0  │\n├───┼───┼─────┤\n│ 1 │ 0 │  0  │\n├───┼───┼─────┤\n│ 1 │ 1 │  1  │\n└───┴───┴─────┘\n```\n\n> NOTE: the `--gate` option handles both, built-in gates by name, and custom gates from HDL files.\n\nFrom Node the specification of a built-in gate is exposed via `Spec` option on the gate class:\n\n```js\nconst hdl = require('hdl-js');\n\nconst {And} = hdl.emulator.BuiltInGates;\n\nconsole.log(And.Spec);\n\n/*\n\nOutput:\n\n{\n  description: 'Implements bitwise 1-bit And & operation.',\n\n  inputPins: ['a', 'b'],\n\n  outputPins: ['out'],\n\n  truthTable: [\n    {a: 0, b: 0, out: 0},\n    {a: 0, b: 1, out: 0},\n    {a: 1, b: 0, out: 0},\n    {a: 1, b: 1, out: 1},\n  ]\n}\n\n*/\n```\n\n### Specifying output format\n\nUsing `--format` option it is possible to control the format of the input/output values. For example, the truth table of the `And16` gate in binary (default), and hexadecimal formats:\n\n```\n./bin/hdl-js --gate And16 --describe\n```\n\nBinary output format:\n\n```\n┌──────────────────┬──────────────────┬──────────────────┐\n│      a[16]       │      b[16]       │     out[16]      │\n├──────────────────┼──────────────────┼──────────────────┤\n│ 0000000000000000 │ 0000000000000000 │ 0000000000000000 │\n├──────────────────┼──────────────────┼──────────────────┤\n│ 0000000000000000 │ 1111111111111111 │ 0000000000000000 │\n├──────────────────┼──────────────────┼──────────────────┤\n│ 1111111111111111 │ 1111111111111111 │ 1111111111111111 │\n├──────────────────┼──────────────────┼──────────────────┤\n│ 1010101010101010 │ 0101010101010101 │ 0000000000000000 │\n├──────────────────┼──────────────────┼──────────────────┤\n│ 0011110011000011 │ 0000111111110000 │ 0000110011000000 │\n├──────────────────┼──────────────────┼──────────────────┤\n│ 0001001000110100 │ 1001100001110110 │ 0001000000110100 │\n└──────────────────┴──────────────────┴──────────────────┘\n```\n\nWith `--format hex`:\n\n```\n./bin/hdl-js --gate And16 --describe --format hex\n```\n\nHexadecimal output format:\n\n```\n┌───────┬───────┬─────────┐\n│ a[16] │ b[16] │ out[16] │\n├───────┼───────┼─────────┤\n│ 0000  │ 0000  │  0000   │\n├───────┼───────┼─────────┤\n│ 0000  │ FFFF  │  0000   │\n├───────┼───────┼─────────┤\n│ FFFF  │ FFFF  │  FFFF   │\n├───────┼───────┼─────────┤\n│ AAAA  │ 5555  │  0000   │\n├───────┼───────┼─────────┤\n│ 3CC3  │ 0FF0  │  0CC0   │\n├───────┼───────┼─────────┤\n│ 1234  │ 9876  │  1034   │\n└───────┴───────┴─────────┘\n```\n\n### Columns whitelist\n\nUsing the `--columns` (`-c`) option it is possible to specify a _whitelist_ of columns which should be printed.\n\nFor example, the resulting list of columns of the [examples/MipsAlu16.hdl](https://github.com/DmitrySoshnikov/hdl-js/blob/master/examples/MipsAlu16.hdl) gate is quite large, and shows a lot of internal pins (such as `cout1`, `cout2`, etc). Often it is desirable to view only needed columns of interest:\n\n```\nhdl-js -g examples/MipsAlu16.hdl -e '[{a: 2, b: 3, op: 2}]' -f dec -c a,b,out\n```\n\nAnd the table showing the result for `2 + 3`:\n\n```\nTruth table for data:\n\n┌───────┬───────┬─────────┐\n│ a[16] │ b[16] │ out[16] │\n├───────┼───────┼─────────┤\n│   2   │   3   │    5    │\n└───────┴───────┴─────────┘\n```\n\n### Testing gates on passed data\n\nIt is possible to manually test and evaluate the outputs of a gate based on its inputs:\n\n```js\nconst hdl = require('hdl-js');\n\nconst {\n  emulator: {\n\n    /**\n     * `Pin` class is used to define inputs, and outputs.\n     */\n    Pin,\n\n    BuiltInGates: {\n      And,\n    }\n  }\n} = hdl;\n\nconst and = new And({\n  inputPins: [\n    new Pin({name: 'a', value: 1}),\n    new Pin({name: 'b', value: 1}),\n  ],\n\n  outputPins: [\n    new Pin({name: 'out'}),\n  ],\n});\n\n// Run the logic.\nand.eval();\n\n// Check \"out\" pin value:\nconsole.log(and.getOutputPins()[0].getValue()); // 1\n```\n\nInput and output pins can also be passed as _plain objects_, rather than as `Pin` instances:\n\n```js\nconst hdl = require('hdl-js');\n\nconst {\n  And,\n  And16,\n} = hdl.emulator.BuiltInGates;\n\n// Simple names:\n\nconst and1 = new And({\n  inputPins: ['a', 'b'],\n  outputPins: ['out'],\n});\n\nand1.setPinValues({a: 1, b: 0});\nand1.eval();\n\nconsole.log(and1.getPin('out').getValue()); // 0\n\n// Spec with values and sizes:\n\nconst and2 = new And16({\n  inputPins: [\n    {name: 'a', size: 16, value: 1},\n    {name: 'b', size: 16, value: 0},\n  ],\n  outputPins: [\n    {name: 'out', size: 16},\n  ],\n});\n\nand2.eval();\nconsole.log(and2.getPin('out').getValue()); // 0\n```\n\n### Pins\n\nAs mentioned above, `Pin`s are used to define _inputs_ and _outputs_ of gates. A single pin represents a _wire_, on which a signal can be transmitted. Logically, a pin can store a _number_ of a needed _size_.\n\nFor example, a pin of size 16 (default is size 1, i.e. a single \"wire\"):\n\n```js\nconst hdl = require('hdl-js');\n\nconst {\n  emulator: {\n    Pin,\n  }\n} = hdl;\n\nconst p1 = new Pin({\n  value: 'p',\n  size: 16,\n});\n\np1.setValue(255);\nconsole.log(p1.getValue()); // 255\n```\n\nUsually when creating a gate instance, explicit usage of the `Pin` class can be omitted (they are created automatically behind the scene), however, it is possible to get a needed pin using `getPin(name)` method on a gate. Then one can get a value of the pin, or subscribe to its `'change'` event.\n\n#### Pin size and ranges\n\nA pin can be of a needed size. For example, in HDL:\n\n```\nIN sel[3];\n```\n\ntells that the maximum value of the `sel` pin is 3 bits (`0b111`), or _\"3 wires\"_.\n\nIndividual bits in HDL can be accessed with direct indices (as in the `sel[2]`), or using _range_ notation (as with the `sel[0..1])`:\n\n```\nMux4Way16(..., sel=sel[0..1], ...)\nMux16(..., sel=sel[2], ...);\n```\n\nIn JS, the individual bits can be manipulated using `setValueAt`, `getRange`, and other methods:\n\n```js\n...\n\nconst p1 = new Pin({\n  value: 'p',\n  size: 3,\n  value: 0,\n});\n\np1.setValue(0b111); // 7\n\nconsole.log(p1.getValueAt(1)); // 1\n\np1.setValueAt(1, 0);\nconsole.log(p1.getValueAt(1)); // 0\n\nconsole.log(p1.getValue()); // 0b101, i.e. 5\nconsole.log(p1.getRange(0, 1)); // first 2 bits: 0b01\n```\n\n#### Pin events\n\nAll `Pin` instances emit the following events:\n\n- `change(newValue, oldValue, fromIndex, toIndex)` - an event emitted whenever a pin changes its value.\n\nIf the `fromIndex` is passed, this means a specific bit was updated, e.g. `a[2]`. If both, `fromIndex`, and `toIndex` are passed, this means a _range_ was updated, e.g. `a[1..3]`. Otherwise, the whole value was updated.\n\n```js\n...\n\nconst p1 = new Pin({\n  value: 'p',\n  size: 16,\n  value: 0,\n});\n\np1.on('change', (newValue, oldValue) => {\n  console.log(`p1 changed from ${oldValue} to ${newValue}.`);\n});\n\np1.setValue(255);\n\n/*\n\nOutput:\n\np1 changed from 0 to 255.\n\n*/\n```\n\n#### Connecting pins together\n\nA pin can be a _value source_ for another pin. By connecting (output of) one pin to the (input of) another pin, we can automate handling of the `'change'` event of the destination pin:\n\n```js\n...\n\nconst a = new Pin({name: 'a', size: 16});\nconst b = new Pin({name: 'b', size: 16});\n\n// Connect `a` to `b`. The `b` pin now listens\n// to the 'change' event of the `a` pin:\n\na.connectTo(b);\n\na.setValue(15);\nconsole.log(b.getValue()); // 15\n\n// Disconnect:\na.disconnectFrom(b);\n\na.setValue(20);\nconsole.log(b.getValue()); // still, 15\n```\n\nIt is also possible to provide a _specification_ for value updates, which may include updates for indices and ranges:\n\n```js\n...\n\n// Auto-connect to: b[2] = a[3]\n\na.connectTo(b, {\n  sourceSpec: {index: 3},\n  destinationSpec: {index: 2},\n});\n\na.setValueAt(3, 1);\nconsole.log(b.getValueAt(2)); // 1\n\n// Disconnect:\na.disconnectFrom(b);\n\n// Connect for range: b[4..7] = a[0..3]\n\na.connectTo(b, {\n  sourceSpec: {range: {from: 0, 3}},\n  destinationSpec: {range: {from: 4, 7}},\n});\n\na.setRange(0, 3, 0b1010);\nconsole.log(b.getRange(4, 7)); // 0b1010;\n```\n\n> **NOTE:** the pin connections are used when creating [composite gates from HDL](#building-chips-in-hdl).\n\n### Creating gates from default spec\n\nAll gates known their own specification, so we can omit passing explicit pins info, and use `defaultFromSpec` method:\n\n```js\nconst hdl = require('.');\n\nconst {And} = hdl.emulator.BuiltInGates;\n\n// Creates input `a` and `b` pins, and\n// ouput `out` pin automatically:\n\nconst and = And.defaultFromSpec();\n\nand\n  .setPinValues({a: 1, b: 0})\n  .eval();\n\nconsole.log(and.getPin('out').getValue()); // 0\n```\n\n### Exec on set of data\n\nIt is also possible to execute and test gate logic on the set of data:\n\n```js\n// const and = new And({ ... });\n\n// Test the gate on set of inputs, get the results\n// for the outputs.\n\nconst inputData = [\n  {a: 1, b: 0},\n  {a: 1, b: 1},\n];\n\nconst {result} = and.execOnData(inputData);\n\nconsole.log(result);\n\n/*\n\nOutput for `result`:\n\n[\n  {a: 1, b: 0, out: 0},\n  {a: 1, b: 1, out: 1},\n]\n\n*/\n```\n\n### Validating passed data on gate logic\n\nIn addition, if _output pins_ are passed, the `execOnData` will validates them, and report conflicting pins, if the expected values differ from the actual ones:\n\n\n```js\n// const and = new And({ ... });\n\n// Pass the output pins as well:\n\nconst data = [\n  {a: 1, b: 0, out: 1}, // invalid output\n  {a: 1, b: 1, out: 1}, // valid\n];\n\nlet {\n  result,\n  conflicts,\n} = and.execOnData(data);\n\n// Result is a correct truth table:\nconsole.log(result);\n\n/*\n\nOutput for `result`:\n\n[\n  {a: 1, b: 0, out: 0},\n  {a: 1, b: 1, out: 1},\n]\n\n*/\n\n// Conflicts contain conflicting entries: {row, pins}.\nconsole.log(conflicts);\n\n/*\n\nConflicts output:\n\n[\n  {\n    row: 0,\n    pins: {\n      out: {\n        expected: 1,\n        actual: 0,\n      },\n    },\n  },\n]\n\n*/\n```\n\nFrom the CLI it's controlled via the `--exec-on-data` (`-e`) option.\n\nIn the example below we validate the gate logic, passing (incorrect in this case) expected value for the `out` pin of the `Or` gate:\n\n```\n./bin/hdl-js -g Or -e '[{\"a\": 1, \"b\": 1, \"out\": 0}]'\n\nFound 1 conflicts in:\n\n  - row: 0, pins: out\n\n┌───┬───┬───────┐\n│ a │ b │  out  │\n├───┼───┼───────┤\n│ 1 │ 1 │ 0 / 1 │\n└───┴───┴───────┘\n```\n\nIt is possible using actual number values in binary (`0b1111`), hexadecimal (`0xF`), and decimal (`15`) formats. Otherwise, the values have to be passed as strings (`'FFFF'` for `0xFFFF`) with correct `--format` option:\n\n```\n./bin/hdl-js -g Not16 -e '[{in: 0xFFFF}]' -f hex\n```\n\nOutput:\n\n```\nTruth table for data:\n\n┌────────┬─────────┐\n│ in[16] │ out[16] │\n├────────┼─────────┤\n│  FFFF  │  0000   │\n└────────┴─────────┘\n```\n\n### Data files for execution\n\nThe `--exec-on-data` (`-e`) option besides accepting the raw data-strings, also accepts _filenames_ which contain the actual data in the _extended JSON_ format. It allows moving the testing data into a separate file, instead of passing the data each time in the command line.\n\nExample `~/my-data.dat`:\n\n```js\n[\n  {a: 1},\n  {a: 1, b: 1},\n  {b: 1},\n]\n```\n\nNow we can apply this _partial data_ on any gate which works with `a` and `b` inputs (for example, `And` gate), and get the calculated results:\n\n```\nhdl-js --gate And --exec-on-data ~/my-data.dat\n\nTruth table for data:\n\n┌───┬───┬─────┐\n│ a │ b │ out │\n├───┼───┼─────┤\n│ 1 │ 0 │  0  │\n├───┼───┼─────┤\n│ 1 │ 1 │  1  │\n├───┼───┼─────┤\n│ 0 │ 1 │  0  │\n└───┴───┴─────┘\n```\n\nAs we can see, if some pins are not provided, they are defaulted to `0`.\n\nThe same data file applied on the `Or` gate, with the corresponding result:\n\n```\nhdl-js --gate Or --exec-on-data ~/my-data.dat\n\nTruth table for data:\n\n┌───┬───┬─────┐\n│ a │ b │ out │\n├───┼───┼─────┤\n│ 1 │ 0 │  1  │\n├───┼───┼─────┤\n│ 1 │ 1 │  1  │\n├───┼───┼─────┤\n│ 0 │ 1 │  1  │\n└───┴───┴─────┘\n```\n\n### Gates scripting\n\nThe `--exec-on-data` [described above](#validating-passed-data-on-gate-logic) provides only _basic functionality_ for gates testing: you just define expected result in the _declarative_ form, and let the gate execute on data.\n\nFor an _advanced_ gates testing, we can use _scripting_, which is an _imperative_ approach for validating chips logic.\n\n> **NOTE**: the scripts format is compatible with the [nand2tetris](http://nand2tetris.org/) course.\n\nThe script files have a simple syntax, support different simulator commands (such as `eval`, `tick`, `tock`, etc), and also looping constructs like `while`, and `repeat`.\n\n#### Executing scripts\n\nScript files usually have `.tst` extension, and automatically load needed chips. As a script executes, it validates the outputs with the specified _compare file_ (which usually has `.cmp` extension). As a side effect script produces the `.out` file.\n\nFor example, the [And.tst](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/scripting/examples/And.tst) script has corresponding [And.cmp](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/scripting/examples/And.cmp), and produces [And.out](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/scripting/examples/And.out) as the result.\n\nHaving the `And.tst`:\n\n```\nload And.hdl,\noutput-file And.out,\ncompare-to And.cmp,\noutput-list a%B3.1.3 b%B3.1.3 out%B3.1.3;\n\nset a 0,\nset b 0,\neval,\noutput;\n\nset a 0,\nset b 1,\neval,\noutput;\n\nset a 1,\nset b 0,\neval,\noutput;\n\nset a 1,\nset b 1,\neval,\noutput;\n```\n\nWe can execute it using the `--script` (`-s`) option:\n\n```\nhdl-js --script src/emulator/hardware/scripting/examples/And.tst\n```\n\nOutput:\n\n```\n✓ Script executed successfully!\n```\n\nIf we have an error in the expected [And.cmp](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/scripting/examples/And.cmp) data, say on line 3:\n\n```\n|   0   |   1   |   1   |\n```\n\nWe'll get the following report:\n\n```\nError executing the script:\n\n   Expected on line 3 of src/emulator/hardware/scripting/examples/And.cmp:\n\n     1 |   a   |   b   |  out  |\n       |  ...\n     3 |   0   |   1   |   1   |\n\n   Received:\n\n     1 |   a   |   b   |  out  |\n       |  ...\n     3 |   0   |   1   |   0   |\n```\n\nIn the example above the testing data itself is invalid. Usually though you'll have a correct testing data, and in case of an invalid gate logic, will receive a report on errors in the specific parts.\n\nIt is also possible to test the whole directory, passing the directory name instead of an individual `.tst` file. In this case, the directory is scanned for all `.tst` files, which are executed in sequence:\n\n```\nhdl-js --script src/emulator/hardware/scripting/examples/n2t/03/\n```\n\nResult:\n\n```\n[PASS] Bit.tst\n[PASS] PC.tst\n[PASS] RAM16K.tst\n[PASS] RAM4K.tst\n[PASS] RAM512.tst\n[PASS] RAM64.tst\n[PASS] RAM8.tst\n[PASS] Register.tst\n```\n\n#### Script controller commands\n\nAll script commands are divided into _Controller commands_, and _Emulator commands_. The former control the scripts execution, the later operates on the loaded chip.\n\nThe basic controller commands are:\n\n- `load <gate-name>` -- loads needed gate (built-in, or from an hdl-file)\n- `output-file <out-file>` -- file created as a side effect of execution\n- `compare-to <compare-file>` -- file to compare to\n- `output-list <columns-format>` -- format of the table columns in the output file, supports `B` (binary), `X` (hexadecimal), `D` (decimal), and `S` (string) columns\n- `echo <string>` -- prints a string\n- `output` -- prints a line to the output file with the current values on gate pins\n\nExample of a script header with the basic controller commands:\n\n```\nload And.hdl,\noutput-file And.out,\ncompare-to And.cmp,\noutput-list a%B3.1.3 b%B3.1.3 out%B3.1.3;\n```\n\nThe `output-list` contains 3 columns (`a`, `b`, and `out`), each in binary (`B`) format, with needed padding on left, middle, and right.\n\nLooping controller commands are:\n\n- `repeat <times> { <commands> }` -- execute a loop needed amount of times\n- `while <condition> { <commands> }` -- a while loop executes until the condition is met\n\nExamples:\n\n```\nrepeat 5 {\n  tick, tock;\n}\n\nwhile RAM[1] <> %B101 {\n  set RAM[1] 5,\n  ticktock;\n}\n```\n\n#### Script emulator commands\n\nThe emulator commands operate on a loaded gate, and include:\n\n- `set <name> <value>` -- sets a value of a needed pin or name\n- `eval` -- evaluates the logic on currently set pins\n- `tick`, `tock`, `ticktock` -- executes appropriate events on the [System clock](#clock)\n\nExample for the `And.hdl`:\n\n```\nset a 0,\nset b 0,\neval,\noutput;\n```\n\n### Sequential run\n\nWhen the `--run` (`-r`) command is passed, it is possible to analyze how the pin values change in time (especially for the clocked gates). This options work with both, `--exec-on-data` (`-e`), and `--describe` (`-d`).\n\nHere's an example running the `Register` truth table:\n\n```\n./bin/hdl-js --gate Register --describe --run\n```\n\nWhich executes the gate in time:\n\n<p align=\"center\">\n  <img src=\"http://dmitrysoshnikov.com/wp-content/uploads/2018/01/Register-run.gif\" alt=\"Register run\" width=\"600\" />\n<p/>\n\n### Gate events\n\nAll gates emit events, which correspond to their internal logic handlers:\n\n- `eval` -- an event happening on evaluation of the compositional logic\n- `clockUp(value)` -- an event happening, when a gate handled the [clock](#clock)'s _rising edge_ (aka \"tick\")\n- `clockDown(value)` -- an event happening, when a gate handled the [clock](#clock)'s _falling edge_ (aka \"tock\")\n\nHere's an example, how an external observer may subscribe to gate logic events:\n\n```js\nconst hdl = require('.');\n\nconst {\n  emulator: {\n    BuiltInGates: {\n      Register,\n    },\n    Clock: {\n      SystemClock,\n    },\n  },\n} = hdl;\n\nconst r1 = Register.defaultFromSpec();\n\n// Handle the event, when `r1` gets its output value:\n\nr1.on('clockDown', () => {\n  console.log(`r1 = ${r1.getPin('out').getValue()}`); // 255\n});\n\n// Setup the `r1` inputs, on the falling edge (clockDown)\n// the value is set to the `out` pin:\n\nr1.setPinValues({\n  in: 255,\n  load: true,\n});\n\n// Run the full clock cycle:\n\nSystemClock\n  .reset()\n  .cycle();\n```\n\n> **NOTE:** as described in [Pins](#pins) section, it is also possible to subscribe to `'change'` event of individual pins.\n\n### Main chip groups\n\nAll gates are grouped into the following categories:\n\n#### Very basic chips\n\nThis group includes two gates which can be used to build _anything else_.\n\n- [Nand](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Nand.js) (negative-And)\n- [Nor](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Nor.js) (negative-Or)\n\nFor example, as was shown above, the basic `And` chip can be built on top of two connected `Nand` gates:\n\n```\nCHIP And {\n  IN a, b;\n  OUT out;\n\n  PARTS:\n\n  Nand(a=a, b=b, out=n);\n  Nand(a=n, b=n, out=out);\n}\n```\n\n#### Basic chips\n\nThe basic group of chips includes primitive building blocks for more complex chips. The basic chips themselves are built from the [very basic chips](#very-basic-chips). The group includes:\n\n- [And](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/And.js)\n- [And16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/And16.js)\n- [Or](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Or.js)\n- [Or16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Or16.js)\n- [Or8Way](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Or8Way.js)\n- [Nor16Way](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Nor16Way.js)\n- [Not](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Not.js)\n- [Not16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Not16.js)\n- [Xor](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Xor.js)\n- [Mux](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Mux.js) (multiplexer)\n- [Mux16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Mux16.js)\n- [Mux4Way16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Mux4Way16.js)\n- [Mux8Way16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Mux8Way16.js)\n- [DMux](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/DMux.js) (demultiplexer)\n- [DMux4Way](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/DMux4Way.js)\n- [DMux8Way](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/DMux8Way.js)\n\nFor example, the more complex [HalfAdder](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/HalfAdder.js) chip can be built on top of `Xor`, and `And` gates:\n\n```\nCHIP HalfAdder {\n  IN a, b;    // 1-bit inputs\n  OUT sum,    // Right bit of a + b\n      carry;  // Left bit of a + b\n\n  PARTS:\n\n  Xor(a=a, b=b, out=sum);\n  And(a=a, b=b, out=carry);\n}\n```\n\nThe `Mux` (multiplexer) gate, which provides basic _selection_ (or _\"if\"_ operation), and being a basic chip, can itself be built from other basic chips from this group, such as `Not`, `And`, and `Or`.\n\nTo see the _full specification_ and _truth table_ of a needed gate, use `--describe` (`-d`) option from CLI.\n\n#### ALU\n\nThe _arithmetic-logic unit_ is an abstraction which encapsulates inside several operations, implemented as smaller sub-chips. Usually ALU accepts two numbers, and based on the _OpCode (operation code)_, evaluates needed result. This group of chips includes:\n\n- [HalfAdder](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/HalfAdder.js) (2 bits adder)\n- [FullAdder](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/FullAdder.js) (3 bits adder)\n- [Add16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Add16.js)\n- [Inc16](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Inc16.js)\n- [ALU](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/ALU.js)\n\nThe ALU chip itself evaluates both, arithmetic (such as addition), and logic (such as `And`, `Or`, etc) operations.\n\n#### Memory chips\n\nThe basic building block for memory chips is a [Flip-Flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)). In particular, in this specific case, it's the _DFF (Data/Delay Flip-Flop)_.\n\nOn top of `DFF` other storage chips, such as 1 `Bit` abstraction, or 16-bit `Register` abstraction, are built. The group includes the following chips:\n\n- [DFF](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/DFF.js) (Data/Delay Flip-Flop)\n- [Bit](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Bit.js) (1-bit memory unit)\n- [Register](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Register.js) (16-bit memory unit)\n- [ARegister](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/ARegister.js) (Address Register)\n- [DRegister](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/DRegister.js) (Data Register)\n- [PC](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/PC.js) (Program Counter)\n- [RAM](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/RAM.js) (Random Access Memory)\n- [RAM8](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/RAM8.js)\n- [RAM64](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/RAM64.js)\n- [RAM512](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/RAM512.js)\n- [RAM4K](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/RAM4K.js)\n- [RAM16K](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/RAM16K.js)\n\nMemory chips are synchronized by the [clock](https://en.wikipedia.org/wiki/Clock_signal), and operate on _rising_ and _falling_ edges of the [clock cycle](https://en.wikipedia.org/wiki/Clock_rate). Specification, and truth table of such chips contains `$clock` information, where negative values (e.g. `-0`) mean low logical level, and positive (`+0`) -- high logical level, or the rising edge.\n\nThe _internal state_ of a clocked chip can _only_ change on the _rising edge_. While the _output_ is _committed_ (usually to reflect the internal state) on the _falling edge_ of the clock. This _delay_ of the output is exactly reflected in the DFF, that is _Delay_ Flip-Flop, name.\n\nSee detailed clock description in the next section.\n\n#### Interface chips\n\nThe interface chips include the gates, which allow communicating to user input and output. These are:\n\n- [Screen](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Screen.js) (video memory)\n- [Keyboard](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Keyboard.js)\n\n##### Screen\n\nThe `Screen` chip represents 256 x 512 video memory, implemented with 8K registers. The gate can manipulate individual pixels using `getPixelAt`, and `setPixelAt` methods.\n\n```js\n...\n\nconst screen = Screen\n  .defaultFromSpec()\n  .clear();\n\nconsole.log(screen.getPixelAt(1, 16)); // 0\n\nscreen.setPixelAt(/* row */ 1,  /* column */ 16, 1);\n\nconsole.log(screen.getPixelAt(1, 16)); // 1\n\n```\n\n##### Keyboard\n\nThe `Keyboard` chip is special, and requires callers to implement the actual keyboard listener, depending on a system where the chip is used. Such caller listeners should call `Keyboard.emit('key', key)` event, and the key code is propagated to the output pin:\n\nExample using from a browser environment:\n\n```js\n...\n\nconst keyboard = Keyboard.defaultFromSpec();\n\nkeyboard.getPin('out').on('change', value => {\n  console.log('Char code: ' + value);\n});\n\ndocument.body.addEventListener('keypress', event => {\n  Keyboard.emit('key', event.key);\n});\n```\n\nThe `Keyboard` also provides default (blocking) `listen` method, which spawns Node's `stdin` keyboard listening:\n\n```js\n...\n\nconst keyboard = Keyboard.defaultFromSpec();\n\nkeyboard.getPin('out').on('change', value => {\n  console.log('Char code: ' + value);\n});\n\n// Listen to stdin.\nkeyboard.listen();\n```\n\nWe can introspect keyboard events using `--describe` option of the `Keyboard` gate:\n\n```\nhdl-js --gate Keyboard --describe\n```\n\nResult:\n\n```\nBuiltIn \"Keyboard\" gate:\n\nDescription:\n\n  A keyboard, implemented as a 16 bit register that stores\n  the currently pressed key code.\n\nInputs:\n\n    Keyboard input\n\nOutputs:\n\n  - out[16]\n\nTruth table: press any key...\n\n┌──────┬─────┐\n│ char │ out │\n├──────┼─────┤\n│  A   │ 65  │\n└──────┴─────┘\n\nCtrl-c to exit...\n```\n\n### Clock\n\nThe _System clock_ is used to synchronize clocked chips (see example above in [memory chips](#memory-chips)).\n\nA clock operates on the [clock rate](https://en.wikipedia.org/wiki/Clock_rate), that is, _number of cycles per second_, measured in **Hz**. The higher the clock rate, the faster machine is.\n\nClock's runtime consists of _cycles_, and _clock cycle_ has two phases: _rising edge_ (aka \"tick\"), and _falling edge_ (aka \"tock\").\n\n<p align=\"center\">\n  <img src=\"http://dmitrysoshnikov.com/wp-content/uploads/2018/01/hdl-js-system-clock-1024x302.png\" alt=\"Clock image\" width=\"700\" />\n<p/>\n\nAs mentioned in the [memory chips](#memory-chips) section, all clocked gates can change their internal state _only on the rising edge_. And on the falling edge they _commit_ the value form the state to the output pins.\n\nFor example, running the:\n\n```\nhdl-js --gate Bit --describe\n```\n\nShows the clock information:\n\n```\n\"Bit\" gate:\n\nDescription:\n\n  1 bit memory register.\n\n  If load[t]=1 then out[t+1] = in[t] else out does not change.\n\n  Clock rising edge updates internal state from the input,\n  if the `load` is set; otherwise, preserves the state.\n\n    ↗ : state = load ? in : state\n\n  Clock falling edge propagates the internal state to the output:\n\n    ↘ : out = state\n\nInputs:\n\n  - in\n  - load\n\nOutputs:\n\n  - out\n\nTruth table:\n\n┌────────┬────┬──────┬─────┐\n│ $clock │ in │ load │ out │\n├────────┼────┼──────┼─────┤\n│   -0   │ 0  │  0   │  0  │\n├────────┼────┼──────┼─────┤\n│   +0   │ 1  │  1   │  0  │\n├────────┼────┼──────┼─────┤\n│   -1   │ 1  │  0   │  1  │\n├────────┼────┼──────┼─────┤\n│   +1   │ 1  │  0   │  1  │\n├────────┼────┼──────┼─────┤\n│   -2   │ 1  │  0   │  1  │\n├────────┼────┼──────┼─────┤\n│   +2   │ 0  │  1   │  1  │\n├────────┼────┼──────┼─────┤\n│   -3   │ 0  │  0   │  0  │\n└────────┴────┴──────┴─────┘\n```\n\nFrom Node the `Clock` is available on the `emulator` object, and we can also get access to the global singleton `SystemClock`, which is used to synchronize the clocked chips:\n\n```js\nconst hdl = require('hdl-js');\n\nconst {\n  emulator: {\n    Clock,\n    Pin,\n  },\n} = hdl;\n\nconst clock = new Clock({rate: 10, value: -5});\nconst pin = new Pin({name: 'a'});\n\n// Track clock events.\nclock.on('tick', value => pin.setValue(value));\n\nclock.tick();\n\nconsole.log(pin.getValue()); // +5;\n```\n\n#### Clock events\n\nThe clock emits the following events:\n\n- `tick` - rising edge\n- `tock` - falling edge\n- `next` - half cycle (`tick` or `tock`)\n- `cycle` - full cycle (`tick` -> `tock`)\n- `change` - clock value change\n\nAll the clocked gates are automatically subscribed to `SystemClock` events, and update the value of their `$clock` pin:\n\n```js\nconst hdl = require('hdl-js');\n\nconst {\n  emulator: {\n    Gate,\n    Clock: {\n      SystemClock,\n    },\n  },\n} = hdl;\n\nclass MyGate extends Gate {\n  static isClocked() {\n    return true;\n  }\n\n  eval() {\n    // Noop, handle only clock signal.\n    return;\n  }\n\n  clockUp(clockValue) {\n    console.log('Handle rising edge:', clockValue);\n  }\n\n  clockDown(clockValue) {\n    console.log('Handle falling edge:', clockValue);\n  }\n}\n\nMyGate.Spec = {\n  inputPins: ['a'],\n  outputPins: ['b'],\n};\n\nconst gate = MyGate.defaultFromSpec();\n\n// Run full clock cycle.\nSystemClock.cycle();\n\n/*\n\nOutput:\n\nHandle rising edge: 0\nHandle falling edge: -1\n\n*/\n```\n\nIt is also possible to `start`, `stop`, and `reset` the clock:\n\n```js\nconst hdl = require('hdl-js');\n\nconst {\n  emulator: {\n    Clock: {\n      SystemClock,\n    },\n  },\n} = hdl;\n\n// Reset the clock:\nSystemClock.reset();\n\n// Subscribe to the events:\n\nSystemClock.on('tick', value => console.log('tick:', value));\nSystemClock.on('tock', value => console.log('tock:', value));\n\n// Run it:\nSystemClock.start();\n\n/*\n\nOutput (every second):\n\ntick: +0\ntock: -1\ntick: +1\ntock: -2\ntick: +2\ntock: -3\n...\n\n*/\n```\n\n#### Clock rate\n\nThe `--clock-rate` parameter controls the rate of the System clock. For example, the second run executes operations faster:\n\nWith default clock rate 1:\n\n```\n./bin/hdl-js --gate Register --describe --run\n```\n\nWith clock rate 3:\n\n```\n./bin/hdl-js --gate Register --describe --run --clock-rate 3\n```\n\n### Composite gates\n\nThe _composite gates_ are created from other, more primitive, gates. By connecting inputs and outputs of the internal chips, it is possible to build an _abstraction_ in a view of a resulting component, which encapsulates inside details of smaller sub-parts.\n\nAlthough it is possible to create a composite gate manually using `CompositeGate` class from `emulator`, usually they are created via HDL.\n\n#### Building chips in HDL\n\nWe already discussed briefly [format of the HDL](#format-of-an-hdl-file), and here we show how to create custom chips, building them from smaller blocks.\n\nAs mentioned, two [very basic gates](#very-basic-chips), the [Nand](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Nand.js), and [Nor](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/Nor.js), can be used to build everything else in the computer chips.\n\nIn the example below, we use the `Nand` gate to implement a custom version of the `And` gate (even though the [built-in And](https://github.com/DmitrySoshnikov/hdl-js/blob/master/src/emulator/hardware/builtin-gates/And.js) gate implementation exists):\n\n```\n// File: examples/And.hdl\n\nCHIP And {\n  IN a, b;\n  OUT out;\n\n  PARTS:\n\n  Nand(a=a, b=b, out=n);\n  Nand(a=n, b=n, out=out);\n}\n```\n\nHere we connect two `Nand` gates in needed order, patching the output of the first one (via the _internal pin_ `n`) to the inputs of the second `Nand` gate.\n\nFrom a user perspective, the _interface_ of our `And` gate looks as follows:\n\n<p align=\"center\">\n  <img src=\"http://dmitrysoshnikov.com/wp-content/uploads/2018/01/and-gate-interface.png\" alt=\"And gate interface\" width=\"400\" />\n<p/>\n\nWhile if we look under the hood of the `And` gate _implementation_, we'll see the following picture:\n\n<p align=\"center\">\n  <img src=\"http://dmitrysoshnikov.com/wp-content/uploads/2018/01/and-gate-implementation.png\" alt=\"And gate implementation\" width=\"400\" />\n<p/>\n\n> **NOTE:** as in other systems, in hardware chips there might be _multiple implementations_ for the _same interface_. E.g. we could build the `And` chip using `Nor` gates, instead of `Nand`.\n\nSo how does it work? The `Nand` stands for \"negative-And\" (or \"not-And\"). And first we feed our own `a` and `b` inputs to the first internal `Nand` chip, and get the \"nand-result\", saving it to the temporary (internal) pin `n`:\n\n```\nNand(a=a, b=b, out=n);\n```\n\nAs you can see, the `Nand` itself defines its inputs as `a`, and `b`, and output as `out`, which is propagated to our internal `n`.\n\n> **NOTE:** run `hdl-js --gate Nand --describe` to see its specification.\n\nThen, if to feed _the same value_ to `Nand` chip, we get the \"Not\" operation -- and that exactly what we do in the second `Nand` \"call\", feeding the value of `n` to both, `a`, and `b` inputs:\n\n```\nNand(a=n, b=n, out=out);\n```\n\nThe resulting `out` from the second `Nand` is fed further to our own `out` [pin](#pin). Eventually we got \"not-not-And\", and what is just \"And\":\n\n```\nNot(Nand(a, b)) == And(a, b)\n```\n\n> **NOTE:** you can also get more details on the implementation in the wonderful [nand2tetris](http://nand2tetris.org/) course by Noam Nisan and Shimon Schocken.\n\n#### Viewing composite gate specification\n\nGetting a specification of a composite gate from HDL doesn't differ from getting the specification of a built-in chip, since the `--gate` option handles both gate types.\n\nFor example, to view the specification of our custom `And` gate from above (see also [examples/And.hdl](https://github.com/DmitrySoshnikov/hdl-js/blob/master/examples/And.hdl)), we can just use the same `--describe` (`-d`) option:\n\n```\nhdl-js --gate examples/And.hdl --describe\n```\n\nWhat results to:\n\n```\nCustom \"And\" gate:\n\nDescription:\n\n  Compiled from HDL composite Gate class \"And\".\n\nInputs:\n\n  - a\n  - b\n\nInternal pins:\n\n  - n\n\nOutputs:\n\n  - out\n\nTruth table:\n\n┌───┬───┬───┬─────┐\n│ a │ b │ n │ out │\n├───┼───┼───┼─────┤\n│ 0 │ 0 │ 1 │  0  │\n├───┼───┼───┼─────┤\n│ 0 │ 1 │ 1 │  0  │\n├───┼───┼───┼─────┤\n│ 1 │ 0 │ 1 │  0  │\n├───┼───┼───┼─────┤\n│ 1 │ 1 │ 0 │  1  │\n└───┴───┴───┴─────┘\n```\n\nAs we can see, it correctly determined our internal pin `n`, and even showed it in the generated truth table.\n\n> **NOTE:** for 1-bit values the generated truth table shows all values. For larger pins, e.g. with size 16, a table with 5 random rows is shown. Try running the `hdl-js -g examples/Not16.hdl -d`.\n\nThe truth table allows us also to check, whether our implementation in the `PARTS` section is correct (and it really is in this case!).\n\nAs an alternative, check also the specification of the built-in `And` gate -- you'll notice that it doesn't differ much, resulting to the same truth table for inputs and outputs.\n\nAnd of course it is possible to do a [sequential run](#sequential-run) of a custom gate too:\n\n```\nhdl-js --gate examples/Not16.hdl --describe --run\n```\n\n#### Using custom and built-in gates in implementation\n\nIn the example above, we used built-in native `Nand` gate to implement our own version of the `And` gate. However, once you have implemented some custom gate, you are free to use it further as a _building block_ for _even more abstracted chips_.\n\nFor example, if we look at the [examples/Mux.hdl](https://github.com/DmitrySoshnikov/hdl-js/blob/master/examples/Mux.hdl) file:\n\n```\n/**\n * Multiplexor:\n * out = a if sel == 0\n *       b otherwise\n */\n\nCHIP Mux {\n  IN a, b, sel;\n  OUT out;\n\n  PARTS:\n\n  Not(in=sel, out=nel);\n  And(a=a, b=nel, out=A);\n  And(a=b, b=sel, out=B);\n  Or(a=A, b=B, out=out);\n}\n```\n\nAssuming the `Mux.hdl` file is in the same directory as the `And.hdl`, the `And` gate in the implementation is loaded exactly from our local _custom_ implementation. Whereas, the `Not`, and `Or` are loaded from the built-ins. If we remove `And.hdl` from this directory, it will also be loaded from built-ins then.\n\nSometimes you may need to override local HDL-implementation, and use an explicit built-in gate in your call. For this we can use `BUILTIN` directive, which specifies that a particular chip call (or the whole gate definition) should be loaded from a corresponding built-in gate.\n\nExample of providing the full backend for this chip:\n\n```\nChip And {\n  IN a, b;\n  OUT out;\n\n  // Delegate fully implementation of this chip\n  // to the built-in `And` chip.\n  BUILTIN And;\n}\n```\n\nExample of overriding just some parts:\n\n```\nChip Nand {\n  IN a, b;\n  OUT out;\n\n  PARTS:\n\n  And(a=a, b=b, out=a_and_b);\n  Not(in=a_and_b, out=out);\n\n  BUILTIN And;\n}\n```\n\nIn the example above the `And` gate in the implementation explicitly marked as a built-in, whereas the `Not` gate will be loaded from local HDL (if it exists). This might be very useful at debugging, when you need to exclude potential issues in you local version of `And` gate, and fall-back to the built-in version. Once you have successfully debugged the problem, you can restore loading `And` from local HDL version.\n\n#### Loading HDL chips from Node\n\nIn Node it is possible to load a composite HDL gate class using the `HDLClassFactory` module, which is exposed on the `emulator`. The `hdl-js` itself also exposes two convenient wrappers: `fromHDLFile`, and `fromHDL`:\n\n```js\nconst hdl = require('hdl-js');\n\n// Load `And` class from HDL:\nconst And = hdl.fromHDLFile('./examples/And.hdl');\n\n// Instance of the class:\nconst and = And.defaultFromSpec();\n\n// Test:\nand\n  .setPinValues({a: 1, b: 1})\n  .eval();\n\n// {a: 1, b: 1, n: 0, out: 1}\nconsole.log(and.getPinValues());\n```\n\n## Code generator\n\nThe _code generator_ module allows _exporting to HDL_ files from gate structures in other forms: from AST, from a composite gate instance, etc.\n\nIn general case it's an inverse procedure to parsing. In the simplest case you have a parsed AST, and the code generator can build an HDL code from it.\n\n### Exporting from AST\n\nHaving an AST of a gate, it is possible to generate an HDL code for it using the `generator` module. It is also possible to do some manipulations and transformations on this AST prior the generation:\n\n```js\nconst {\n  parser,\n  generator,\n} = require('hdl-js');\n\nconst originalHDL = `\n  CHIP And {\n    IN a, b;\n    OUT out;\n\n    PARTS:\n\n    Nand(a=a, b=b, out=n);\n    Nand(a=n, b=n, out=out);\n  }\n`;\n\n// Obtain the AST.\nconst ast = parser.parse(originalHDL);\n\n// Slightly transform, reimplementing the second\n// part as direct `Not` instead of `Nand`:\n\nconst {parts} = ast;\n\n// Not(in=n, out=out);\nparts[1] = {\n  type: 'ChipCall',\n  name: 'Not',\n  arguments: [\n    // First argument: `in=n`\n    {\n      type: 'Argument',\n      name: {type: 'Name', value: 'in'},\n      value: {type: 'Name', value: 'n'},\n    },\n    // Take second argument from the original call: `out=out`\n    parts[1].arguments[2],\n  ],\n};\n\n// Finally, generate the HDL code:\n\nconst exportedHDL = generator.fromAST(ast);\n\nconsole.log(exportedHDL);\n\n/*\n\nResult:\n\nCHIP And {\n  IN a, b;\n  OUT out;\n\n  PARTS:\n\n  Nand(a=a, b=b, out=n);\n  Not(in=n, out=out);\n}\n\n*/\n```\n\n### Exporting from Composite Gates\n\nComposite gates are usually created in the _declarative style_ [using HDL](#building-chips-in-hdl) syntax. Alternatively, one may need to create a composite gate directly in the _imperative style_, i.e. manually creating pins, connecting them together, etc.\n\nIn the example below we manually create a composite gate, and export it to HDL file:\n\n> **NOTE**: the _preferred way_ of creating composite gates is still using declarative HDL notation. Use manual imperative style only in unusual programmatic cases.\n\n```js\nconst hdl = require('hdl-js');\n\nconst {\n  generator,\n  emulator: {\n    CompositeGate,\n    Pin,\n    BuiltInGates: {\n      And,\n      Not,\n    },\n  },\n} = hdl;\n\n/*\n\nWe create manually (imperatively) a composite gate, corresponding\nto the following declarative definition in HDL:\n\nCHIP MyGate {\n  IN x[16], y[16];\n  OUT out[16];\n\n  PARTS:\n\n  And(a=x[0], b=y[0], out=temp);\n  Not(in=temp, out=out[1]);\n}\n\n*/\n\n// Inputs:\nconst x = new Pin({name: 'x', size: 16});\nconst y = new Pin({name: 'y', size: 16});\n\n// Outputs:\nconst out = new Pin({name: 'out', size: 16});\n\n// Internal pins:\nconst temp = new Pin({name: 'temp'});\n\n// Parts:\nconst and = And.defaultFromSpec();\nconst not = Not.defaultFromSpec();\n\n// Now connect needed pins to each other,\n// creating a connection graph:\n\n// ----------------------------------\n// And(a=x[0], b=y[0], out=temp);\n\n// a=x[0]\nx.connectTo(and.getPin('a'), {\n  sourceSpec: {index: 0},\n});\n\n// b=y[0]\ny.connectTo(and.getPin('b'), {\n  sourceSpec: {index: 0},\n});\n\n// out=temp\nand.getPin('out').connectTo(temp);\n\n// ----------------------------------\n// Not(in=temp, out=out[1]);\n\n// in=temp\ntemp.connectTo(not.getPin('in'));\n\n// out=out[1]\nnot.getPin('out').connectTo(out, {\n  destinationSpec: {index: 1},\n});\n\n// Create our gate instance:\nconst myGate = new CompositeGate({\n  name: 'myGate',\n  inputPins: [x, y],\n  outputPins: [out],\n  internalPins: [temp],\n  parts: [and, not],\n});\n\n// Finally, export this composite gate to an AST\n// structure, and generate HDL code:\n\nconst hdlCode = generator.fromCompositeGate(myGate);\n\nconsole.log(hdlCode);\n\n/*\n\nResult:\n\nCHIP MyGate {\n  IN x[16], y[16];\n  OUT out[16];\n\n  PARTS:\n\n  And(a=x[0], b=y[0], out=temp);\n  Not(in=temp, out=out[1]);\n}\n\n*/\n```\n","maintainers":[{"name":"dmitrysoshnikov","email":"dmitry.soshnikov@gmail.com"}],"time":{"modified":"2022-05-04T19:24:54.708Z","created":"2017-12-11T04:38:14.202Z","0.0.1":"2017-12-11T04:38:14.202Z","0.0.2":"2017-12-12T07:14:55.900Z","0.0.3":"2017-12-14T02:07:14.415Z","0.0.4":"2017-12-22T06:26:18.580Z","0.0.5":"2017-12-24T23:10:05.870Z","0.0.6":"2017-12-26T01:06:04.418Z","0.0.7":"2017-12-26T09:12:36.550Z","0.0.8":"2017-12-27T03:48:03.822Z","0.0.9":"2017-12-28T07:13:19.772Z","0.0.10":"2017-12-28T19:17:01.820Z","0.0.11":"2017-12-29T07:49:46.940Z","0.0.12":"2017-12-30T08:07:53.463Z","0.0.13":"2018-01-05T01:11:50.678Z","0.0.14":"2018-01-08T22:30:16.840Z","0.0.15":"2018-01-09T06:46:29.692Z","0.0.16":"2018-01-10T09:11:10.388Z","0.0.17":"2018-01-12T00:35:48.827Z","0.0.18":"2018-01-12T05:07:38.473Z","0.0.19":"2018-01-12T05:09:33.456Z","0.0.20":"2018-01-15T01:04:08.973Z","0.0.21":"2018-01-15T01:59:06.084Z","0.0.22":"2018-01-15T02:04:17.218Z","0.0.23":"2018-01-17T20:19:18.602Z","0.0.24":"2018-01-18T21:02:50.827Z","0.0.25":"2018-01-19T01:48:05.905Z","0.0.26":"2018-01-19T07:24:08.109Z","0.0.27":"2018-01-19T21:12:15.106Z","0.0.28":"2018-01-20T02:04:53.907Z","0.0.29":"2018-01-22T06:24:19.489Z","0.0.30":"2018-01-22T07:53:52.985Z","0.0.31":"2018-01-22T08:11:08.988Z","0.0.32":"2018-01-25T10:08:40.580Z","0.0.33":"2018-01-25T10:12:18.191Z","0.0.34":"2018-01-25T20:50:31.083Z","0.0.35":"2018-01-26T02:21:13.978Z","0.0.36":"2018-01-28T03:34:20.561Z","0.0.37":"2018-02-02T00:38:07.365Z","0.0.38":"2018-02-02T01:22:43.371Z","0.0.39":"2018-02-02T06:02:14.481Z","0.0.40":"2018-02-02T08:20:37.673Z","0.0.41":"2018-02-02T20:16:46.491Z","0.0.42":"2018-02-05T03:47:40.543Z","0.0.43":"2018-02-05T05:42:30.770Z","0.0.44":"2018-02-08T01:38:36.887Z","0.0.45":"2018-02-08T18:17:00.628Z","0.0.46":"2018-02-18T04:12:57.441Z","0.0.47":"2018-02-18T05:50:32.302Z","0.0.48":"2018-02-19T20:17:42.450Z","0.0.49":"2018-02-19T23:14:32.950Z","0.0.50":"2018-02-23T22:02:17.219Z","0.0.51":"2018-02-26T19:31:02.843Z","0.0.52":"2018-02-27T04:53:23.402Z","0.0.53":"2018-02-27T04:56:20.057Z","0.0.54":"2018-02-27T19:15:51.923Z","0.0.55":"2018-02-27T20:50:02.073Z","0.0.56":"2018-02-28T00:12:47.968Z","0.0.57":"2018-03-01T21:15:30.277Z","0.0.58":"2018-03-02T00:05:19.413Z","0.0.59":"2018-03-10T06:31:03.564Z","0.0.60":"2018-03-10T06:39:38.435Z","0.0.61":"2018-03-17T20:04:40.381Z","0.0.62":"2018-03-18T00:58:04.596Z","0.0.63":"2018-03-18T01:06:22.001Z","0.0.64":"2018-03-18T04:11:56.891Z","0.0.65":"2018-03-18T04:37:37.859Z","0.0.66":"2018-03-19T08:31:20.376Z","0.0.67":"2018-03-20T06:15:18.364Z","0.0.68":"2018-03-20T20:33:37.317Z","0.0.69":"2018-03-28T06:03:33.610Z","0.0.70":"2018-04-07T23:46:03.909Z","0.0.71":"2018-04-07T23:53:07.878Z","0.0.72":"2018-06-12T03:09:08.291Z"},"homepage":"https://github.com/DmitrySoshnikov/hdl-js","keywords":["HDL","Hardware","Emulator","Boolean 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