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netlist","homepage":"https://github.com/nturley/netlistsvg#readme","keywords":["svg","netlist"],"repository":{"type":"git","url":"git+https://github.com/nturley/netlistsvg.git"},"author":{"name":"Neil Turley"},"bugs":{"url":"https://github.com/nturley/netlistsvg/issues"},"license":"MIT","readme":"[![Linux Build Status](https://travis-ci.org/nturley/netlistsvg.svg?branch=master)](https://travis-ci.org/nturley/netlistsvg)\n[![Windows Build status](https://ci.appveyor.com/api/projects/status/heijuq5nhw9m7rib/branch/master?svg=true)](https://ci.appveyor.com/project/nturley/netlistsvg/branch/master)\n[![Gitter chat](https://badges.gitter.im/nturley/netlistsvg.png)](https://gitter.im/netlistsvg)\n[![npm version](https://badge.fury.io/js/netlistsvg.svg)](https://badge.fury.io/js/netlistsvg)\n![npm](https://img.shields.io/npm/dm/netlistsvg.svg)\n\n# netlistsvg\ndraws an SVG schematic from a [yosys](https://github.com/cliffordwolf/yosys) JSON netlist. This can be generated [the `write_json` command](http://www.clifford.at/yosys/cmd_json.html). It uses [elkjs](https://github.com/OpenKieler/elkjs) for layout.\n\nYou can see an online demo [here](https://nturley.github.io/netlistsvg)\n\n# Installation/Usage Instructions\n\n## Command Line Interface\nInstall nodejs if isn't already installed\n```\nnpm install -g netlistsvg\n```\n\nYou can execute netlistsvg like this.\n```\nnetlistsvg input_json_file [-o output_svg_file] [--skin skin_file]\n```\nThe default value for the output file is out.svg.\n\nShould work on Linux, OSX, and Windows. Running the build scripts (makefiles and the web demo) is easiest on Linux and OSX.\n\n## Web bundle\n\nI have a web bundle hosted on github pages here: https://nturley.github.io/netlistsvg/built/netlistsvg.bundle.js\nIt doesn't wrap ELKjs, so you'll need to include it separately. ELK creates a global variable, so you'll need to include ELKjs before netlistsvg.\n\nIn HTML it would look something like this\n```html\n<script type=\"text/javascript\" src=\"https://nturley.github.io/netlistsvg/elk.bundled.js\"></script>\n<script type=\"text/javascript\" src=\"https://nturley.github.io/netlistsvg/built/netlistsvg.bundle.js\"></script>\n```\n\nOn ObservableHQ, you can require it like this.\n\n```javascript\nnetlistsvg = {\n  var ELK = await require('https://nturley.github.io/netlistsvg/elk.bundled.js')\n  window.ELK = ELK\n  return require('https://nturley.github.io/netlistsvg/built/netlistsvg.bundle.js')\n}\n```\n\nYou may want to download and host your own copy.\n\nThe web bundle includes both the analog and digital skin and an example netlist for each. Using a promise would look like this.\n```javascript\nawait netlistsvg.render(netlistsvg.digitalSkin, netlistsvg.exampleDigital);\n```\nOr to log the result to console using the callback API:\n```javascript\nnetlistsvg.render(netlistsvg.digitalSkin, netlistsvg.exampleDigital, (err, result) => console.log(result));\n```\n\nTo turn Verilog into YosysJSON in the browser, you can use [YosysJS](http://www.clifford.at/yosys/yosysjs.html)\n\n# Examples\n\nHere's an digital netlist produced by Yosys along with the diagram that netlistsvg created from it.\n<details>\n  <summary>JSON Source</summary>\n\n```json\n{\n  \"modules\": {\n    \"up3down5\": {\n      \"ports\": {\n        \"clock\": {\n          \"direction\": \"input\",\n          \"bits\": [ 2 ]\n        },\n        \"data_in\": {\n          \"direction\": \"input\",\n          \"bits\": [ 3, 4, 5, 6, 7, 8, 9, 10, 11 ]\n        },\n        \"up\": {\n          \"direction\": \"input\",\n          \"bits\": [ 12 ]\n        },\n        \"down\": {\n          \"direction\": \"input\",\n          \"bits\": [ 13 ]\n        },\n        \"carry_out\": {\n          \"direction\": \"output\",\n          \"bits\": [ 14 ]\n        },\n        \"borrow_out\": {\n          \"direction\": \"output\",\n          \"bits\": [ 15 ]\n        },\n        \"count_out\": {\n          \"direction\": \"output\",\n          \"bits\": [ 16, 17, 18, 19, 20, 21, 22, 23, 24 ]\n        },\n        \"parity_out\": {\n          \"direction\": \"output\",\n          \"bits\": [ 25 ]\n        }\n      },\n      \"cells\": {\n        \"$add$input.v:17$3\": {\n          \"type\": \"$add\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 16, 17, 18, 19, 20, 21, 22, 23, 24 ],\n            \"B\": [ \"1\", \"1\" ],\n            \"Y\": [ 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ]\n          }\n        },\n        \"$and$input.v:28$5\": {\n          \"type\": \"$and\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 12 ],\n            \"B\": [ 35 ],\n            \"Y\": [ 36 ]\n          }\n        },\n        \"$and$input.v:29$6\": {\n          \"type\": \"$and\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 13 ],\n            \"B\": [ 37 ],\n            \"Y\": [ 38 ]\n          }\n        },\n        \"$procdff$40\": {\n          \"type\": \"$dff\",\n          \"port_directions\": {\n            \"CLK\": \"input\",\n            \"D\": \"input\",\n            \"Q\": \"output\"\n          },\n          \"connections\": {\n            \"CLK\": [ 2 ],\n            \"D\": [ 39, 40, 41, 42, 43, 44, 45, 46, 47 ],\n            \"Q\": [ 16, 17, 18, 19, 20, 21, 22, 23, 24 ]\n          }\n        },\n        \"$procdff$41\": {\n          \"type\": \"$dff\",\n          \"port_directions\": {\n            \"CLK\": \"input\",\n            \"D\": \"input\",\n            \"Q\": \"output\"\n          },\n          \"connections\": {\n            \"CLK\": [ 2 ],\n            \"D\": [ 36 ],\n            \"Q\": [ 14 ]\n          }\n        },\n        \"$procdff$42\": {\n          \"type\": \"$dff\",\n          \"port_directions\": {\n            \"CLK\": \"input\",\n            \"D\": \"input\",\n            \"Q\": \"output\"\n          },\n          \"connections\": {\n            \"CLK\": [ 2 ],\n            \"D\": [ 38 ],\n            \"Q\": [ 15 ]\n          }\n        },\n        \"$procdff$43\": {\n          \"type\": \"$dff\",\n          \"port_directions\": {\n            \"CLK\": \"input\",\n            \"D\": \"input\",\n            \"Q\": \"output\"\n          },\n          \"connections\": {\n            \"CLK\": [ 2 ],\n            \"D\": [ 48 ],\n            \"Q\": [ 25 ]\n          }\n        },\n        \"$procmux$36\": {\n          \"type\": \"$pmux\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"S\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 16, 17, 18, 19, 20, 21, 22, 23, 24 ],\n            \"B\": [ 26, 27, 28, 29, 30, 31, 32, 33, 34, 49, 50, 51, 52, 53, 54, 55, 56, 57, 3, 4, 5, 6, 7, 8, 9, 10, 11 ],\n            \"S\": [ 58, 59, 60 ],\n            \"Y\": [ 39, 40, 41, 42, 43, 44, 45, 46, 47 ]\n          }\n        },\n        \"$procmux$37_CMP0\": {\n          \"type\": \"$eq\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 13, 12 ],\n            \"B\": [ \"0\", \"1\" ],\n            \"Y\": [ 58 ]\n          }\n        },\n        \"$procmux$38_CMP0\": {\n          \"type\": \"$eq\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 13, 12 ],\n            \"B\": [ \"1\", \"0\" ],\n            \"Y\": [ 59 ]\n          }\n        },\n        \"$procmux$39_CMP0\": {\n          \"type\": \"$eq\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 13, 12 ],\n            \"B\": [ \"0\", \"0\" ],\n            \"Y\": [ 60 ]\n          }\n        },\n        \"$reduce_xor$input.v:27$4\": {\n          \"type\": \"$reduce_xor\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 39, 40, 41, 42, 43, 44, 45, 46, 47 ],\n            \"Y\": [ 48 ]\n          }\n        },\n        \"$sub$input.v:16$2\": {\n          \"type\": \"$sub\",\n          \"port_directions\": {\n            \"A\": \"input\",\n            \"B\": \"input\",\n            \"Y\": \"output\"\n          },\n          \"connections\": {\n            \"A\": [ 16, 17, 18, 19, 20, 21, 22, 23, 24 ],\n            \"B\": [ \"1\", \"0\", \"1\" ],\n            \"Y\": [ 49, 50, 51, 52, 53, 54, 55, 56, 57, 37 ]\n          }\n        }\n      }\n    }\n  }\n}\n```\n</details>\n\n![example](https://raw.githubusercontent.com/nturley/netlistsvg/master/doc/up3down5.svg?sanitize=true)\n\nYou can also write out the JSON by hand, of course. We support [JSON5](https://json5.org) syntax.\n\nHere's an analog example.\n\n<details>\n  <summary>JSON Source</summary>\n\n```json\n{\n  \"modules\": {\n    \"resistor_divider\": {\n      \"ports\": {\n        \"A\": {\n          \"direction\": \"input\",\n          \"bits\": [2]\n        },\n        \"B\": {\n          \"direction\": \"input\",\n          \"bits\": [3]\n        },\n        \"A AND B\": {\n          \"direction\": \"output\",\n          \"bits\": [4]\n        }\n      },\n      \"cells\": {\n        \"R1\": {\n          \"type\": \"r_v\",\n          \"connections\": {\n            \"A\": [2],\n            \"B\": [5]\n          },\n          \"attributes\": {\n            \"value\":\"10k\"\n          }\n        },\n        \"R2\": {\n          \"type\": \"r_v\",\n          \"connections\": {\n            \"A\": [3],\n            \"B\": [5]\n          },\n          \"attributes\": {\n            \"value\":\"10k\"\n          }\n        },\n        \"Q1\": {\n          \"type\": \"q_pnp\",\n          \"port_directions\": {\n            \"C\": \"input\",\n            \"B\": \"input\",\n            \"E\": \"output\"\n          },\n          \"connections\": {\n            \"C\": [6],\n            \"B\": [5],\n            \"E\": [7]\n          }\n        },\n        \"R3\": {\n          \"type\": \"r_v\",\n          \"connections\": {\n            \"A\": [7],\n            \"B\": [8]\n          },\n          \"attributes\": {\n            \"value\":\"10k\"\n          }\n        },\n        \"R4\": {\n          \"type\": \"r_v\",\n          \"connections\": {\n            \"A\": [7],\n            \"B\": [9]\n          },\n          \"attributes\": {\n            \"value\":\"10k\"\n          }\n        },\n        \"R5\": {\n          \"type\": \"r_v\",\n          \"connections\": {\n            \"A\": [4],\n            \"B\": [12]\n          },\n          \"attributes\": {\n            \"value\":\"10k\"\n          }\n        },\n        \"Q2\": {\n          \"type\": \"q_pnp\",\n          \"port_directions\": {\n            \"C\": \"input\",\n            \"B\": \"input\",\n            \"E\": \"output\"\n          },\n          \"connections\": {\n            \"C\": [10],\n            \"B\": [9],\n            \"E\": [4]\n          }\n        },\n        \"vcc\": {\n          \"type\": \"vcc\",\n          \"connections\": {\n            \"A\": [6]\n          },\n          \"attributes\": {\n            \"name\":\"VCC\"\n          }\n        },\n        \"vcc2\": {\n          \"type\": \"vcc\",\n          \"connections\": {\n            \"A\": [10]\n          },\n          \"attributes\": {\n            \"name\":\"VCC\"\n          }\n        },\n        \"gnd\": {\n          \"type\": \"gnd\",\n          \"port_directions\": {\n            \"A\": \"input\"\n          },\n          \"connections\": {\n            \"A\": [8]\n          },\n          \"attributes\": {\n            \"name\":\"DGND\"\n          }\n        },\n        \"gnd2\": {\n          \"type\": \"gnd\",\n          \"port_directions\": {\n            \"A\": \"input\"\n          },\n          \"connections\": {\n            \"A\": [12]\n          },\n          \"attributes\": {\n            \"name\":\"DGND\"\n          }\n        }\n      }\n    }\n  }\n}\n```\n</details>\n\n![example](https://raw.githubusercontent.com/nturley/netlistsvg/master/doc/and.svg?sanitize=true)\n\n## Skin File\nIt pulls the node icons and configuration options from a SVG skin file. This our default digital skin file.\n\n<img src=\"https://raw.githubusercontent.com/nturley/netlistsvg/master/lib/default.svg?sanitize=true\" width=\"800\" height=\"300\">\n\nThis is our analog skin file.\n\n<img src=\"https://raw.githubusercontent.com/nturley/netlistsvg/master/lib/analog.svg?sanitize=true\" width=\"400\" height=\"525\">\n\nA skin file can use style tags or inline CSS to style the elements. That will be copied onto the output file. A skin file also defines a library of components to use. Each component has an alias list. It will use that component as a template for any cell with that type that it encounters. Each component defines the position and id of each of its ports so we know where to attach the wires to.\n\nFor example, here is a mux definition. It has two aliases: \"$pmux\" and \"$mux\". It defines a type name, and a width and height, as well as the position and id of each of it's ports. In general you can rearrange them however you like, and add whatever SVG elements you like inside the template.\n\n```XML\n<g s:type=\"mux\" transform=\"translate(50, 50)\" s:width=\"20\" s:height=\"40\">\n  <s:alias val=\"$pmux\"/>\n  <s:alias val=\"$mux\"/>\n\n  <path d=\"M0,0 L20,10 L20,30 L0,40 Z\"/>\n\n  <g s:x=\"0\" s:y=\"10\" s:pid=\"A\"/>\n  <g s:x=\"0\" s:y=\"30\" s:pid=\"B\"/>\n  <g s:x=\"10\" s:y=\"35\" s:pid=\"S\"/>\n  <g s:x=\"20\" s:y=\"20\" s:pid=\"Y\"/>\n</g>\n```\n\nIn addition to the library of components that are matched to cells, a skin file defines some special nodes. Input/Output ports, constants, Splits/Joins, and the generic node. Splits/Joins and the generic nodes are resized and ports are added or removed to adjust to the cell.\n\nThe elkjs layout properties are also defined in the skin file.\n\n```XML\n<s:layoutEngine\n      org.eclipse.elk.layered.spacing.nodeNodeBetweenLayers=\"5\"\n      org.eclipse.elk.spacing.nodeNode= \"35\"\n      org.eclipse.elk.direction=\"DOWN\"\n    />\n```\nAny properties specified here will get passed along to the layout engine. Node and edge properties aren't configurable (yet).\n\n## Input JSON\nYosys JSON includes more information than we need. We only render one module (either the first or the module with an attribute \"top\"). If the cell name matches one of the aliases of a template from the skin, then it will use it as a template for the SVG file. Port directions are optional for cells that are defined in the skin (not generic cells).\n\nSo it should look something like this.\n```json\n{\n  \"modules\": {\n    \"<dont care>\": {\n      \"ports\": {\n        \"<port name>\": {\n          \"direction\": \"<input|output\",\n          \"bits\": [ 2, \"1\", ... ]\n        },\n        ...\n      },\n      \"cells\": {\n        \"<cell name>\": {\n          \"type\": \"<type name\",\n          \"port_directions\": {\n            \"<port name>\": \"<input|output>\",\n            ...\n          },\n          \"connections\": {\n            \"<port name>\": [ 3, \"0\", ... ],\n            ...\n          }\n      },\n      ...\n    }\n  }\n}\n```\n\n## ElkJS\nELK is using a layered approach (Sugiyama, Ganser), similar to dot in the Graphviz package. You can read about their algorithm here: https://rtsys.informatik.uni-kiel.de/%7Ebiblio/downloads/papers/jvlc13.pdf\n\n# Status\nWe are getting close to the 1.0 release. At that point, the skin file format will be considered specified and breaking changes will only happen on major version bumps.\n\n## Generating `input_json_file` with Yosys\n\n[Yosys from Clifford Wolf](https://github.com/cliffordwolf/yosys) can be used to generate the `input_json_file` using [the `write_json` command](http://www.clifford.at/yosys/cmd_json.html).\n\nUnless you are doing something special you will want to use [the `prep` command](http://www.clifford.at/yosys/cmd_prep.html). Some examples are provided below and you can find some runnable examples which go from Verilog to diagrams in the [examples directory](./examples) (with example Makefile).\n\n#### Generate top level diagram\n\nThis command will generate a diagram of the top module with all the inner modules shown as boxes.\n\n```\nyosys -p \"prep -top my_top_module; write_json output.json\" input.v\n```\n\n#### Generate logic diagram\n\nYou can give it the `-flatten` argument to  [the `prep` command](http://www.clifford.at/yosys/cmd_prep.html) if you want Yosys to convert everything into low level logic. Only basic logic cells and black boxes will exist after flattening.\n\n```\nyosys -p \"prep -top my_top_module -flatten; write_json output.json\" input.v\n```\n\n### Generate AND (or not) and inverter (NOT) diagram\n\nIt is also frequently common that you want to create a diagram only using AND and NOT (or NAND and NOT) cells. ([This is called an AIG](https://en.wikipedia.org/wiki/And-inverter_graph).) This can be done with Yosys' [`aigmap` command](http://www.clifford.at/yosys/cmd_proc.html).\n\n```\nyosys -p \"prep -top my_top_module; aigmap; write_json output.json\" input.v\n```\n","readmeFilename":"README.md"}