lora: REG_FIFO (0x00): 0x68
lora: REG_OP_MODE (0x01): 0x03
lora: REG_FRF_MSB (0x06): 0x6c
lora: REG_FRF_MID (0x07): 0x80
lora: REG_FRF_LSB (0x08): 0x00
lora: REG_PA_CONFIG (0x09): 0x4f
lora: REG_PA_RAMP (0x0a): 0x09
lora: REG_OCP (0x0b): 0x2b
lora: REG_LNA (0x0c): 0x23
lora: REG_FIFO_ADDR_PTR (0x0d): 0x00
lora: REG_FIFO_TX_BASE_ADDR (0x0e): 0x00
lora: REG_FIFO_RX_BASE_ADDR (0x0f): 0x00
lora: REG_FIFO_RX_CURRENT_ADDR (0x10): 0xff
lora: REG_IRQ_FLAGS (0x12): 0x15
lora: REG_RX_NB_BYTES (0x13): 0x0b
lora: REG_RX_HEADER_COUNT_VALUE_MSB (0x14): 0x28
lora: REG_RX_HEADER_COUNT_VALUE_LSB (0x15): 0x0c
lora: REG_RX_PACKET_COUNT_VALUE_MSB (0x16): 0x12
lora: REG_RX_PACKET_COUNT_VALUE_LSB (0x17): 0x47
lora: REG_MODEM_STAT (0x18): 0x32
lora: REG_PKT_SNR_VALUE (0x19): 0x3e
lora: REG_PKT_RSSI_VALUE (0x1a): 0x00
lora: REG_MODEM_CONFIG_1 (0x1d): 0x00
lora: REG_MODEM_CONFIG_2 (0x1e): 0x00
lora: REG_PREAMBLE_MSB (0x20): 0x00
lora: REG_PREAMBLE_LSB (0x21): 0x00
lora: REG_PAYLOAD_LENGTH (0x22): 0x05
lora: REG_MAX_PAYLOAD_LENGTH (0x23): 0x00
lora: REG_HOP_PERIOD (0x24): 0x05
lora: REG_FIFO_RX_BYTE_AD (0x25): 0x00
lora: REG_MODEM_CONFIG_3 (0x26): 0x04
lora: REG_FREQ_ERROR_MSB (0x28): 0x55
lora: REG_FREQ_ERROR_MID (0x29): 0x55
lora: REG_FREQ_ERROR_LSB (0x2a): 0x55
lora: REG_RSSI_WIDEBAND (0x2c): 0x55
lora: REG_DETECTION_OPTIMIZE (0x31): 0x40
lora: REG_INVERT_IQ (0x33): 0x00
lora: REG_DETECTION_THRESHOLD (0x37): 0x00
lora: REG_SYNC_WORD (0x39): 0xf5
lora: REG_DIO_MAPPING_2 (0x40): 0x00
lora: REG_VERSION (0x42): 0x12
lora: REG_TCXO (0x4b): 0x09
lora: REG_PA_DAC (0x4d): 0x84
lora: REG_FORMER_TEMP (0x5b): 0xf4
lora: REG_AGC_REF (0x61): 0x1c
lora: REG_AGC_THRESH_1 (0x62): 0x0e
lora: REG_AGC_THRESH_2 (0x63): 0x5b
lora: REG_AGC_THRESH_3 (0x64): 0xcc
lora: REG_PLL (0x70): 0xd0